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review.coreboot.org / coreboot / c02b4fc9db3c3c1e263027382697b566127f66bb / . / src / mainboard / intel / truxton / mptable.c
blob: 94facfe71774bce7a13ec244ea3877b99c53ba74 [file] [log] [blame]
Ed Swierkb8e53eb2008-10-13 23:18:56 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Arastra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21#include <console/console.h>
22#include <arch/smp/mpspec.h>
23#include <device/pci.h>
24#include <string.h>
25#include <stdint.h>
26
27void *smp_write_config_table(void *v)
28{
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "Intel ";
31 static const char productid[12] = "Truxton ";
32 struct mp_config_table *mc;
33 u8 bus_num;
34 u8 bus_isa;
35 u8 bus_pea0 = 0;
36 u8 bus_pea1 = 0;
37 u8 bus_aioc;
38 device_t dev;
39
40 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
41 memset(mc, 0, sizeof(*mc));
42
43 memcpy(mc->mpc_signature, sig, sizeof(sig));
44 mc->mpc_length = sizeof(*mc); /* initially just the header */
45 mc->mpc_spec = 0x04;
46 mc->mpc_checksum = 0; /* not yet computed */
47 memcpy(mc->mpc_oem, oem, sizeof(oem));
48 memcpy(mc->mpc_productid, productid, sizeof(productid));
49 mc->mpc_oemptr = 0;
50 mc->mpc_oemsize = 0;
51 mc->mpc_entry_count = 0; /* No entries yet... */
52 mc->mpc_lapic = LAPIC_ADDR;
53 mc->mpe_length = 0;
54 mc->mpe_checksum = 0;
55 mc->reserved = 0;
56
57 smp_write_processors(mc);
58
59
60 /* AIOC bridge */
61 dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
62 if (dev) {
63 bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
64 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
65 bus_isa++;
66 }
67 else {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]68 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
Ed Swierkb8e53eb2008-10-13 23:18:56 +0000[diff] [blame]69 bus_aioc = 0;
70 bus_isa = 9;
71 }
72 /* PCIe A0 */
73 dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
74 if (dev) {
75 bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
76 }
77 else {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]78 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
Ed Swierkb8e53eb2008-10-13 23:18:56 +0000[diff] [blame]79 bus_pea0 = 0;
80 }
81 /* PCIe A1 */
82 dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
83 if (dev) {
84 bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
85 }
86 else {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]87 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
Ed Swierkb8e53eb2008-10-13 23:18:56 +0000[diff] [blame]88 bus_pea1 = 0;
89 }
90
91 /* define bus and isa numbers */
92 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
93 smp_write_bus(mc, bus_num, "PCI ");
94 }
95 smp_write_bus(mc, bus_isa, "ISA ");
96
97 /* IOAPIC handling */
98 smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
99
100 /* ISA backward compatibility interrupts */
101 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
102 bus_isa, 0x00, 0x8, 0x00);
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
104 bus_isa, 0x01, 0x8, 0x01);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
106 bus_isa, 0x00, 0x8, 0x02);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
108 bus_isa, 0x03, 0x8, 0x03);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
110 bus_isa, 0x04, 0x8, 0x04);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
112 bus_isa, 0x06, 0x8, 0x06);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
114 bus_isa, 0x08, 0x8, 0x08);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
116 bus_isa, 0x09, 0x8, 0x09);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
118 bus_isa, 0x0c, 0x8, 0x0c);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_isa, 0x0d, 0x8, 0x0d);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_isa, 0x0e, 0x8, 0x0e);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_isa, 0x0f, 0x8, 0x0f);
125
126 /* Standard local interrupt assignments */
127 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_isa, 0x00, MP_APIC_ALL, 0x00);
129 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_isa, 0x00, MP_APIC_ALL, 0x01);
131
132 /* IMCH/IICH PCI devices */
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
134 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
136 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
138 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
140 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
142 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
144 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
145
146 if (bus_pea0) {
147 /* PCIe slot 0 */
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
149 bus_pea0, (0<<2)|0, 0x8, 0x10);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
151 bus_pea0, (0<<2)|1, 0x8, 0x11);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
153 bus_pea0, (0<<2)|2, 0x8, 0x12);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
155 bus_pea0, (0<<2)|3, 0x8, 0x13);
156 }
157
158 if (bus_pea1) {
159 /* PCIe slots 1-4 */
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
161 bus_pea1, (0<<2)|0, 0x8, 0x10);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
163 bus_pea1, (0<<2)|1, 0x8, 0x11);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
165 bus_pea1, (0<<2)|2, 0x8, 0x12);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
167 bus_pea1, (0<<2)|3, 0x8, 0x13);
168 }
169
170 if (bus_aioc) {
171 /* AIOC PCI devices */
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
175 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
177 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
178 }
179
180 /* There is no extension information... */
181
182 /* Compute the checksums */
183 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
184
185 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]186 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
Ed Swierkb8e53eb2008-10-13 23:18:56 +0000[diff] [blame]187 mc, smp_next_mpe_entry(mc));
188 return smp_next_mpe_entry(mc);
189}
190
191unsigned long write_smp_table(unsigned long addr)
192{
193 void *v;
194 v = smp_write_floating_table(addr);
195 return (unsigned long)smp_write_config_table(v);
196}
197