Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/smp/mpspec.h> |
| 3 | #include <device/pci.h> |
| 4 | #include <string.h> |
| 5 | #include <stdint.h> |
| 6 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 7 | void *smp_write_config_table(void *v) |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 8 | { |
| 9 | static const char sig[4] = "PCMP"; |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 10 | static const char oem[8] = "IWILL "; |
| 11 | static const char productid[12] = "DK8X "; |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 12 | struct mp_config_table *mc; |
| 13 | unsigned char bus_num; |
| 14 | unsigned char bus_isa; |
| 15 | unsigned char bus_8131_1; |
| 16 | unsigned char bus_8131_2; |
| 17 | unsigned char bus_8111_1; |
| 18 | |
| 19 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 20 | memset(mc, 0, sizeof(*mc)); |
| 21 | |
| 22 | memcpy(mc->mpc_signature, sig, sizeof(sig)); |
| 23 | mc->mpc_length = sizeof(*mc); /* initially just the header */ |
| 24 | mc->mpc_spec = 0x04; |
| 25 | mc->mpc_checksum = 0; /* not yet computed */ |
| 26 | memcpy(mc->mpc_oem, oem, sizeof(oem)); |
| 27 | memcpy(mc->mpc_productid, productid, sizeof(productid)); |
| 28 | mc->mpc_oemptr = 0; |
| 29 | mc->mpc_oemsize = 0; |
| 30 | mc->mpc_entry_count = 0; /* No entries yet... */ |
| 31 | mc->mpc_lapic = LAPIC_ADDR; |
| 32 | mc->mpe_length = 0; |
| 33 | mc->mpe_checksum = 0; |
| 34 | mc->reserved = 0; |
| 35 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 36 | smp_write_processors(mc); |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 37 | |
| 38 | { |
| 39 | device_t dev; |
| 40 | |
| 41 | /* 8111 */ |
| 42 | dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); |
| 43 | if (dev) { |
| 44 | bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); |
| 45 | bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); |
| 46 | bus_isa++; |
| 47 | } |
| 48 | else { |
| 49 | printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); |
| 50 | |
| 51 | bus_8111_1 = 4; |
| 52 | bus_isa = 5; |
| 53 | } |
| 54 | /* 8131-1 */ |
| 55 | dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); |
| 56 | if (dev) { |
| 57 | bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); |
| 58 | |
| 59 | } |
| 60 | else { |
| 61 | printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); |
| 62 | |
| 63 | bus_8131_1 = 2; |
| 64 | } |
| 65 | /* 8131-2 */ |
| 66 | dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); |
| 67 | if (dev) { |
| 68 | bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); |
| 69 | |
| 70 | } |
| 71 | else { |
| 72 | printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); |
| 73 | |
| 74 | bus_8131_2 = 3; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | /* define bus and isa numbers */ |
| 79 | for(bus_num = 0; bus_num < bus_isa; bus_num++) { |
| 80 | smp_write_bus(mc, bus_num, "PCI "); |
| 81 | } |
| 82 | smp_write_bus(mc, bus_isa, "ISA "); |
| 83 | |
| 84 | /* IOAPIC handling */ |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 85 | smp_write_ioapic(mc, 2, 0x11, 0xfec00000); |
| 86 | { |
| 87 | device_t dev; |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 88 | struct resource *res; |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 89 | /* 8131 apic 3 */ |
| 90 | dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); |
| 91 | if (dev) { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 92 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 93 | if (res) { |
| 94 | smp_write_ioapic(mc, 0x03, 0x11, res->base); |
| 95 | } |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 96 | } |
| 97 | /* 8131 apic 4 */ |
| 98 | dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); |
| 99 | if (dev) { |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 100 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 101 | if (res) { |
| 102 | smp_write_ioapic(mc, 0x04, 0x11, res->base); |
| 103 | } |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 104 | } |
| 105 | } |
| 106 | |
| 107 | /* ISA backward compatibility interrupts */ |
| 108 | smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 109 | bus_isa, 0x00, 0x02, 0x00); |
| 110 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 111 | bus_isa, 0x01, 0x02, 0x01); |
| 112 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 113 | bus_isa, 0x00, 0x02, 0x02); |
| 114 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 115 | bus_isa, 0x03, 0x02, 0x03); |
| 116 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 117 | bus_isa, 0x04, 0x02, 0x04); |
| 118 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 119 | bus_isa, 0x05, 0x02, 0x05); |
| 120 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 121 | bus_isa, 0x06, 0x02, 0x06); |
| 122 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 123 | bus_isa, 0x07, 0x02, 0x07); |
| 124 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 125 | bus_isa, 0x08, 0x02, 0x08); |
| 126 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 127 | bus_isa, 0x09, 0x02, 0x09); |
| 128 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 129 | bus_isa, 0x0a, 0x02, 0x0a); |
| 130 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 131 | bus_isa, 0x0b, 0x02, 0x0b); |
| 132 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 133 | bus_isa, 0x0c, 0x02, 0x0c); |
| 134 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 135 | bus_isa, 0x0d, 0x02, 0x0d); |
| 136 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 137 | bus_isa, 0x0e, 0x02, 0x0e); |
| 138 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 139 | bus_isa, 0x0f, 0x02, 0x0f); |
| 140 | |
| 141 | /* Standard local interrupt assignments */ |
| 142 | smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 143 | bus_isa, 0x00, MP_APIC_ALL, 0x00); |
| 144 | smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 145 | bus_isa, 0x00, MP_APIC_ALL, 0x01); |
| 146 | |
| 147 | |
| 148 | /* PCI Slot 1 */ |
| 149 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 150 | bus_8131_2, (1<<2)|0, 0x02, 0x11); |
| 151 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 152 | bus_8131_2, (1<<2)|1, 0x02, 0x12); |
| 153 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 154 | bus_8131_2, (1<<2)|2, 0x02, 0x13); |
| 155 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 156 | bus_8131_2, (1<<2)|3, 0x02, 0x10); |
| 157 | |
| 158 | /* PCI Slot 2 */ |
| 159 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 160 | bus_8131_2, (2<<2)|0, 0x02, 0x12); |
| 161 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 162 | bus_8131_2, (2<<2)|1, 0x02, 0x13); |
| 163 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 164 | bus_8131_2, (2<<2)|2, 0x02, 0x10); |
| 165 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 166 | bus_8131_2, (2<<2)|3, 0x02, 0x11); |
| 167 | |
| 168 | /* PCI Slot 3 */ |
| 169 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 170 | bus_8131_1, (1<<2)|0, 0x02, 0x11); |
| 171 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 172 | bus_8131_1, (1<<2)|1, 0x02, 0x12); |
| 173 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 174 | bus_8131_1, (1<<2)|2, 0x02, 0x13); |
| 175 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 176 | bus_8131_1, (1<<2)|3, 0x02, 0x10); |
| 177 | |
| 178 | /* PCI Slot 4 */ |
| 179 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 180 | bus_8131_1, (2<<2)|0, 0x02, 0x12); |
| 181 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 182 | bus_8131_1, (2<<2)|1, 0x02, 0x13); |
| 183 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 184 | bus_8131_1, (2<<2)|2, 0x02, 0x10); |
| 185 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 186 | bus_8131_1, (2<<2)|3, 0x02, 0x11); |
| 187 | |
| 188 | /* PCI Slot 5 */ |
| 189 | #warning "FIXME get the irqs right, it's just hacked to work for now" |
| 190 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 191 | bus_8111_1, (5<<2)|0, 0x02, 0x11); |
| 192 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 193 | bus_8111_1, (5<<2)|1, 0x02, 0x12); |
| 194 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 195 | bus_8111_1, (5<<2)|2, 0x02, 0x13); |
| 196 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 197 | bus_8111_1, (5<<2)|3, 0x02, 0x10); |
| 198 | |
| 199 | /* PCI Slot 6 */ |
| 200 | #warning "FIXME get the irqs right, it's just hacked to work for now" |
| 201 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 202 | bus_8111_1, (4<<2)|0, 0x02, 0x10); |
| 203 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 204 | bus_8111_1, (4<<2)|1, 0x02, 0x11); |
| 205 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 206 | bus_8111_1, (4<<2)|2, 0x02, 0x12); |
| 207 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 208 | bus_8111_1, (4<<2)|3, 0x02, 0x13); |
| 209 | |
| 210 | /* On board nics */ |
| 211 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 212 | bus_8131_1, (3<<2)|0, 0x02, 0x13); |
| 213 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, |
| 214 | bus_8131_1, (4<<2)|0, 0x02, 0x13); |
| 215 | |
| 216 | /* There is no extension information... */ |
| 217 | |
| 218 | /* Compute the checksums */ |
| 219 | mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 220 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 221 | printk_debug("Wrote the mp table end at: %p - %p\n", |
| 222 | mc, smp_next_mpe_entry(mc)); |
| 223 | return smp_next_mpe_entry(mc); |
| 224 | } |
| 225 | |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 226 | unsigned long write_smp_table(unsigned long addr) |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 227 | { |
| 228 | void *v; |
| 229 | v = smp_write_floating_table(addr); |
Eric Biederman | 018d8dd | 2004-11-04 11:04:33 +0000 | [diff] [blame] | 230 | return (unsigned long)smp_write_config_table(v); |
Ronald G. Minnich | 2248989 | 2004-01-27 17:08:03 +0000 | [diff] [blame] | 231 | } |
| 232 | |