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review.coreboot.org / coreboot / 22489894e189616bb5694cfed8bd951951e68fae / . / src / mainboard / Iwill / DK8S2 / mptable.c
blob: bd9df2e3ac63e4ba114e774e0961bb26a37ac3c5 [file] [log] [blame]
Ronald G. Minnich22489892004-01-27 17:08:03 +0000[diff] [blame^]1#include <console/console.h>
2#include <arch/smp/mpspec.h>
3#include <device/pci.h>
4#include <string.h>
5#include <stdint.h>
6
7void *smp_write_config_table(void *v, unsigned long * processor_map)
8{
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "LNXI ";
11 static const char productid[12] = "HDAMA ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_8131_1;
16 unsigned char bus_8131_2;
17 unsigned char bus_8111_1;
18
19 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
20 memset(mc, 0, sizeof(*mc));
21
22 memcpy(mc->mpc_signature, sig, sizeof(sig));
23 mc->mpc_length = sizeof(*mc); /* initially just the header */
24 mc->mpc_spec = 0x04;
25 mc->mpc_checksum = 0; /* not yet computed */
26 memcpy(mc->mpc_oem, oem, sizeof(oem));
27 memcpy(mc->mpc_productid, productid, sizeof(productid));
28 mc->mpc_oemptr = 0;
29 mc->mpc_oemsize = 0;
30 mc->mpc_entry_count = 0; /* No entries yet... */
31 mc->mpc_lapic = LAPIC_ADDR;
32 mc->mpe_length = 0;
33 mc->mpe_checksum = 0;
34 mc->reserved = 0;
35
36 smp_write_processors(mc, processor_map);
37
38 {
39 device_t dev;
40
41 /* 8111 */
42 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
43 if (dev) {
44 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
45 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
46 bus_isa++;
47 }
48 else {
49 printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
50
51 bus_8111_1 = 4;
52 bus_isa = 5;
53 }
54 /* 8131-1 */
55 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
56 if (dev) {
57 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
58
59 }
60 else {
61 printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
62
63 bus_8131_1 = 2;
64 }
65 /* 8131-2 */
66 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
67 if (dev) {
68 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
69
70 }
71 else {
72 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
73
74 bus_8131_2 = 3;
75 }
76 }
77
78 /* define bus and isa numbers */
79 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
80 smp_write_bus(mc, bus_num, "PCI ");
81 }
82 smp_write_bus(mc, bus_isa, "ISA ");
83
84 /* IOAPIC handling */
85
86 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
87 {
88 device_t dev;
89 uint32_t base;
90 /* 8131 apic 3 */
91 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
92 if (dev) {
93 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
94 base &= PCI_BASE_ADDRESS_MEM_MASK;
95 smp_write_ioapic(mc, 0x03, 0x11, base);
96 }
97 /* 8131 apic 4 */
98 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
99 if (dev) {
100 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
101 base &= PCI_BASE_ADDRESS_MEM_MASK;
102 smp_write_ioapic(mc, 0x04, 0x11, base);
103 }
104 }
105
106 /* ISA backward compatibility interrupts */
107 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
108 bus_isa, 0x00, 0x02, 0x00);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
110 bus_isa, 0x01, 0x02, 0x01);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
112 bus_isa, 0x00, 0x02, 0x02);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
114 bus_isa, 0x03, 0x02, 0x03);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
116 bus_isa, 0x04, 0x02, 0x04);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
118 bus_isa, 0x05, 0x02, 0x05);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_isa, 0x06, 0x02, 0x06);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_isa, 0x07, 0x02, 0x07);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_isa, 0x08, 0x02, 0x08);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
126 bus_isa, 0x09, 0x02, 0x09);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_isa, 0x0a, 0x02, 0x0a);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_isa, 0x0b, 0x02, 0x0b);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
132 bus_isa, 0x0c, 0x02, 0x0c);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
134 bus_isa, 0x0d, 0x02, 0x0d);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
136 bus_isa, 0x0e, 0x02, 0x0e);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
138 bus_isa, 0x0f, 0x02, 0x0f);
139
140 /* Standard local interrupt assignments */
141 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
142 bus_isa, 0x00, MP_APIC_ALL, 0x00);
143 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
144 bus_isa, 0x00, MP_APIC_ALL, 0x01);
145
146
147 /* PCI Slot 1 */
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
149 bus_8131_2, (1<<2)|0, 0x02, 0x11);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
151 bus_8131_2, (1<<2)|1, 0x02, 0x12);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
153 bus_8131_2, (1<<2)|2, 0x02, 0x13);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
155 bus_8131_2, (1<<2)|3, 0x02, 0x10);
156
157 /* PCI Slot 2 */
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
159 bus_8131_2, (2<<2)|0, 0x02, 0x12);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
161 bus_8131_2, (2<<2)|1, 0x02, 0x13);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
163 bus_8131_2, (2<<2)|2, 0x02, 0x10);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
165 bus_8131_2, (2<<2)|3, 0x02, 0x11);
166
167 /* PCI Slot 3 */
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
169 bus_8131_1, (1<<2)|0, 0x02, 0x11);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
171 bus_8131_1, (1<<2)|1, 0x02, 0x12);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_8131_1, (1<<2)|2, 0x02, 0x13);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
175 bus_8131_1, (1<<2)|3, 0x02, 0x10);
176
177 /* PCI Slot 4 */
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
179 bus_8131_1, (2<<2)|0, 0x02, 0x12);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
181 bus_8131_1, (2<<2)|1, 0x02, 0x13);
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
183 bus_8131_1, (2<<2)|2, 0x02, 0x10);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
185 bus_8131_1, (2<<2)|3, 0x02, 0x11);
186
187 /* PCI Slot 5 */
188#warning "FIXME get the irqs right, it's just hacked to work for now"
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
190 bus_8111_1, (5<<2)|0, 0x02, 0x11);
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
192 bus_8111_1, (5<<2)|1, 0x02, 0x12);
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
194 bus_8111_1, (5<<2)|2, 0x02, 0x13);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
196 bus_8111_1, (5<<2)|3, 0x02, 0x10);
197
198 /* PCI Slot 6 */
199#warning "FIXME get the irqs right, it's just hacked to work for now"
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
201 bus_8111_1, (4<<2)|0, 0x02, 0x10);
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
203 bus_8111_1, (4<<2)|1, 0x02, 0x11);
204 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
205 bus_8111_1, (4<<2)|2, 0x02, 0x12);
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
207 bus_8111_1, (4<<2)|3, 0x02, 0x13);
208
209 /* On board nics */
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
211 bus_8131_1, (3<<2)|0, 0x02, 0x13);
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
213 bus_8131_1, (4<<2)|0, 0x02, 0x13);
214
215 /* There is no extension information... */
216
217 /* Compute the checksums */
218 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
219
220 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
221 printk_debug("Wrote the mp table end at: %p - %p\n",
222 mc, smp_next_mpe_entry(mc));
223 return smp_next_mpe_entry(mc);
224}
225
226unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
227{
228 void *v;
229 v = smp_write_floating_table(addr);
230 return (unsigned long)smp_write_config_table(v, processor_map);
231}
232