Michał Żygowski | fba0830 | 2020-04-13 20:51:32 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/io.h> |
| 4 | #include <device/pnp.h> |
| 5 | #include <stdint.h> |
Michał Żygowski | fba0830 | 2020-04-13 20:51:32 +0200 | [diff] [blame] | 6 | #include <device/pnp_ops.h> |
| 7 | #include "sch5545.h" |
| 8 | |
| 9 | static void pnp_enter_conf_state(pnp_devfn_t dev) |
| 10 | { |
| 11 | unsigned int port = dev >> 8; |
| 12 | outb(0x55, port); |
| 13 | } |
| 14 | |
| 15 | static void pnp_exit_conf_state(pnp_devfn_t dev) |
| 16 | { |
| 17 | unsigned int port = dev >> 8; |
| 18 | outb(0xaa, port); |
| 19 | } |
| 20 | |
| 21 | /* |
| 22 | * Set the BAR / iobase for a specific device. |
| 23 | * pnp_devfn_t dev must be in conf state. |
| 24 | * LDN LPC IF must be active. |
| 25 | */ |
| 26 | static void set_iobase(pnp_devfn_t dev, uint16_t device_addr, uint16_t bar_addr) |
| 27 | { |
| 28 | uint16_t bar; |
| 29 | |
| 30 | /* |
| 31 | * Set the BAR. We have to flip the BAR due to different register layout: |
| 32 | * - LPC addr LSB on device_addr + 2 |
| 33 | * - LPC addr MSB on device_addr + 3 |
| 34 | */ |
| 35 | bar = ((bar_addr >> 8) & 0xff) | ((bar_addr & 0xff) << 8); |
| 36 | pnp_set_iobase(dev, device_addr + 2, bar); |
| 37 | } |
| 38 | |
| 39 | /* |
| 40 | * Set the IRQ for the specific device. |
| 41 | * pnp_devfn_t dev must be in conf state. |
| 42 | * LDN LPC IF must be active. |
| 43 | */ |
| 44 | static void set_irq(pnp_devfn_t dev, uint8_t irq_device, unsigned int irq) |
| 45 | { |
| 46 | if (irq > 15) |
| 47 | return; |
| 48 | |
| 49 | pnp_write_config(dev, SCH5545_IRQ_BASE + irq, irq_device); |
| 50 | } |
| 51 | |
| 52 | /* |
| 53 | * sch5545 has 2 LEDs which are accessed via color (1 bit), 2 bits for a |
| 54 | * pattern blink and 1 bit for "code fetch" which means the cpu/mainboard is |
| 55 | * working (always set). |
| 56 | */ |
| 57 | void sch5545_set_led(unsigned int runtime_reg_base, unsigned int color, uint16_t blink) |
| 58 | { |
| 59 | uint8_t val = blink & SCH5545_LED_BLINK_MASK; |
| 60 | val |= SCH5545_LED_CODE_FETCH; |
| 61 | if (color) |
| 62 | val |= SCH5545_LED_COLOR_GREEN; |
| 63 | outb(val, runtime_reg_base + SCH5545_RR_LED); |
| 64 | } |
| 65 | |
| 66 | void sch5545_early_init(unsigned int port) |
| 67 | { |
| 68 | pnp_devfn_t dev; |
| 69 | |
| 70 | /* Enable SERIRQ */ |
| 71 | dev = PNP_DEV(port, SCH5545_LDN_GCONF); |
| 72 | pnp_enter_conf_state(dev); |
| 73 | pnp_set_logical_device(dev); |
| 74 | pnp_write_config(dev, 0x24, pnp_read_config(dev, 0x24) | 0x04); |
| 75 | |
| 76 | /* Enable LPC interface */ |
| 77 | dev = PNP_DEV(port, SCH5545_LDN_LPC); |
| 78 | pnp_set_logical_device(dev); |
| 79 | pnp_set_enable(dev, 1); |
| 80 | /* Set LPC BAR mask */ |
| 81 | pnp_write_config(dev, SCH5545_BAR_LPC_IF, 0x01); |
| 82 | /* BAR valid, Frame/LDN = 0xc */ |
| 83 | pnp_write_config(dev, SCH5545_BAR_LPC_IF + 1, SCH5545_LDN_LPC | 0x80); |
| 84 | set_iobase(dev, SCH5545_BAR_LPC_IF, port); |
| 85 | |
| 86 | /* Enable Runtime Registers */ |
| 87 | |
| 88 | /* The Runtime Registers BAR is 0x40 long */ |
| 89 | pnp_write_config(dev, SCH5545_BAR_RUNTIME_REG, 0x3f); |
| 90 | /* BAR valid, Frame/LDN = 0xa */ |
| 91 | pnp_write_config(dev, SCH5545_BAR_RUNTIME_REG + 1, SCH5545_LDN_RR | 0x80); |
| 92 | |
| 93 | /* Map Runtime Registers */ |
| 94 | set_iobase(dev, SCH5545_BAR_RUNTIME_REG, SCH5545_RUNTIME_REG_BASE); |
| 95 | dev = PNP_DEV(port, SCH5545_LDN_RR); |
| 96 | pnp_set_logical_device(dev); |
| 97 | pnp_set_enable(dev, 1); |
| 98 | |
| 99 | /* Set LED color and indicate BIOS has reached code fetch phase */ |
| 100 | sch5545_set_led(SCH5545_RUNTIME_REG_BASE, SCH5545_LED_COLOR_GREEN, |
| 101 | SCH5545_LED_BLINK_ON); |
| 102 | |
Michał Żygowski | 3b1d1ce | 2021-11-21 17:00:02 +0100 | [diff] [blame] | 103 | /* |
| 104 | * Clear global PME status and disable PME generation to avoid |
| 105 | * unexpected wakeups or hangs. OS will re-enable it via ACPI. |
| 106 | */ |
| 107 | outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); |
| 108 | outb(1, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_STS); |
| 109 | |
Michał Żygowski | fba0830 | 2020-04-13 20:51:32 +0200 | [diff] [blame] | 110 | /* Configure EMI */ |
| 111 | dev = PNP_DEV(port, SCH5545_LDN_LPC); |
| 112 | pnp_set_logical_device(dev); |
| 113 | /* EMI BAR has 11 registers, but vendor sets the mask to 0xf */ |
| 114 | pnp_write_config(dev, SCH5545_BAR_EM_IF, 0x0f); |
| 115 | /* BAR valid, Frame/LDN = 0x00 */ |
| 116 | pnp_write_config(dev, SCH5545_BAR_EM_IF + 1, SCH5545_LDN_EMI | 0x80); |
| 117 | set_iobase(dev, SCH5545_BAR_EM_IF, SCH5545_EMI_BASE); |
| 118 | |
| 119 | pnp_exit_conf_state(dev); |
| 120 | } |
| 121 | |
| 122 | void sch5545_enable_uart(unsigned int port, unsigned int uart_no) |
| 123 | { |
| 124 | pnp_devfn_t dev; |
| 125 | |
| 126 | if (uart_no > 1) |
| 127 | return; |
| 128 | |
| 129 | /* Configure serial port */ |
| 130 | dev = PNP_DEV(port, SCH5545_LDN_LPC); |
| 131 | pnp_enter_conf_state(dev); |
| 132 | pnp_set_logical_device(dev); |
| 133 | /* Set UART BAR mask to 0x07 (8 registers) */ |
| 134 | pnp_write_config(dev, SCH5545_BAR_UART1 + (4 * uart_no), 0x07); |
| 135 | /* Set BAR valid, Frame/LDN = UART1/2 LDN 0x07/0x08 */ |
| 136 | pnp_write_config(dev, SCH5545_BAR_UART1 + (4 * uart_no) + 1, |
| 137 | (SCH5545_LDN_UART1 + uart_no) | 0x80); |
| 138 | set_iobase(dev, SCH5545_BAR_UART1 + (4 * uart_no), (uart_no == 1) ? 0x2f8 : 0x3f8); |
| 139 | /* IRQ 3 for UART2, IRQ4 for UART1 */ |
| 140 | set_irq(dev, SCH5545_LDN_UART1 + uart_no, 4 - uart_no); |
| 141 | |
| 142 | dev = PNP_DEV(port, SCH5545_LDN_UART1 + uart_no); |
| 143 | pnp_set_logical_device(dev); |
| 144 | pnp_set_enable(dev, 1); |
| 145 | pnp_write_config(dev, SCH5545_UART_CONFIG_SELECT, SCH5545_UART_POWER_VCC); |
| 146 | |
| 147 | pnp_exit_conf_state(dev); |
| 148 | } |
| 149 | |
| 150 | int sch5545_get_gpio(uint8_t sio_port, uint8_t gpio) |
| 151 | { |
| 152 | pnp_devfn_t dev; |
| 153 | uint16_t runtime_reg_base; |
| 154 | uint8_t gpio_bank, gpio_num; |
| 155 | |
| 156 | gpio_bank = gpio / 10; |
| 157 | gpio_num = gpio % 10; |
| 158 | /* |
| 159 | * GPIOs are divided into banks of 8 GPIOs (kind of). Each group starts at decimal |
| 160 | * base, i.e. 8 GPIOs from GPIO000, 8 GPIOs from GPIO010, etc., up to GPIO071 and |
| 161 | * GPIO072 which are an exception (only two GPIOs in the bank 7). |
| 162 | */ |
| 163 | if (gpio_num > 7) |
| 164 | return -1; |
| 165 | else if (gpio_bank == 7 && gpio_num > 1) |
| 166 | return -1; |
| 167 | else if (gpio_bank > 7) |
| 168 | return -1; |
| 169 | |
| 170 | dev = PNP_DEV(sio_port, SCH5545_LDN_LPC); |
| 171 | pnp_enter_conf_state(dev); |
| 172 | pnp_set_logical_device(dev); |
| 173 | |
| 174 | runtime_reg_base = pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 2); |
| 175 | runtime_reg_base |= pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 3) << 8; |
| 176 | |
| 177 | pnp_exit_conf_state(dev); |
| 178 | |
| 179 | if (runtime_reg_base == 0) |
| 180 | return -1; |
| 181 | |
| 182 | outb(gpio_bank * 8 + gpio_num, runtime_reg_base + SCH5545_RR_GPIO_SEL); |
| 183 | |
| 184 | return inb(runtime_reg_base + SCH5545_RR_GPIO_READ) & 1; |
| 185 | } |