Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
Patrick Rudolph | 9f8f115 | 2020-05-06 11:58:45 +0200 | [diff] [blame] | 4 | #include <commonlib/region.h> |
Elyes Haouas | af776d8 | 2022-12-04 09:09:49 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 6 | #include <cpu/intel/em64t101_save_state.h> |
Elyes Haouas | af776d8 | 2022-12-04 09:09:49 +0100 | [diff] [blame] | 7 | #include <cpu/intel/model_206ax/model_206ax.h> |
| 8 | #include <cpu/x86/smm.h> |
| 9 | #include <device/mmio.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <device/pci_ops.h> |
Duncan Laurie | 51cb26d | 2012-06-23 15:22:43 -0700 | [diff] [blame] | 12 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Kyösti Mälkki | 661ad46 | 2020-12-29 06:26:21 +0200 | [diff] [blame] | 13 | #include <soc/nvs.h> |
Vladimir Serbinenko | 4141b47 | 2015-05-16 13:48:10 +0200 | [diff] [blame] | 14 | #include <southbridge/intel/bd82x6x/me.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 15 | #include <southbridge/intel/common/finalize.h> |
Elyes Haouas | af776d8 | 2022-12-04 09:09:49 +0100 | [diff] [blame] | 16 | #include <southbridge/intel/common/gpio.h> |
| 17 | #include <southbridge/intel/common/pmutil.h> |
| 18 | #include <types.h> |
Duncan Laurie | 51cb26d | 2012-06-23 15:22:43 -0700 | [diff] [blame] | 19 | |
Elyes HAOUAS | 74aa99a | 2019-03-16 08:40:06 +0100 | [diff] [blame] | 20 | #include "pch.h" |
Elyes HAOUAS | 74aa99a | 2019-03-16 08:40:06 +0100 | [diff] [blame] | 21 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 22 | static void southbridge_gate_memory_reset_real(int offset, |
| 23 | u16 use, u16 io, u16 lvl) |
| 24 | { |
| 25 | u32 reg32; |
| 26 | |
| 27 | /* Make sure it is set as GPIO */ |
| 28 | reg32 = inl(use); |
| 29 | if (!(reg32 & (1 << offset))) { |
| 30 | reg32 |= (1 << offset); |
| 31 | outl(reg32, use); |
| 32 | } |
| 33 | |
| 34 | /* Make sure it is set as output */ |
| 35 | reg32 = inl(io); |
| 36 | if (reg32 & (1 << offset)) { |
| 37 | reg32 &= ~(1 << offset); |
| 38 | outl(reg32, io); |
| 39 | } |
| 40 | |
| 41 | /* Drive the output low */ |
| 42 | reg32 = inl(lvl); |
| 43 | reg32 &= ~(1 << offset); |
| 44 | outl(reg32, lvl); |
| 45 | } |
| 46 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 47 | /* |
| 48 | * Drive GPIO 60 low to gate memory reset in S3. |
| 49 | * |
| 50 | * Intel reference designs all use GPIO 60 but it is |
| 51 | * not a requirement and boards could use a different pin. |
| 52 | */ |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 53 | void southbridge_gate_memory_reset(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 54 | { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 55 | u16 gpiobase; |
| 56 | |
Angel Pons | 78c45bd | 2021-01-06 02:40:14 +0100 | [diff] [blame] | 57 | gpiobase = pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 58 | if (!gpiobase) |
| 59 | return; |
| 60 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 61 | if (CONFIG_DRAM_RESET_GATE_GPIO >= 32) |
| 62 | southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32, |
| 63 | gpiobase + GPIO_USE_SEL2, |
| 64 | gpiobase + GP_IO_SEL2, |
| 65 | gpiobase + GP_LVL2); |
| 66 | else |
| 67 | southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO, |
| 68 | gpiobase + GPIO_USE_SEL, |
| 69 | gpiobase + GP_IO_SEL, |
| 70 | gpiobase + GP_LVL); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 71 | } |
| 72 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 73 | void southbridge_smi_monitor(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 74 | { |
| 75 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 76 | u32 trap_sts, trap_cycle; |
| 77 | u32 data, mask = 0; |
| 78 | int i; |
| 79 | |
| 80 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 81 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 82 | |
| 83 | trap_cycle = RCBA32(0x1e10); |
| 84 | for (i=16; i<20; i++) { |
| 85 | if (trap_cycle & (1 << i)) |
Kyösti Mälkki | a072043 | 2022-12-03 19:35:53 +0200 | [diff] [blame] | 86 | mask |= (0xff << ((i - 16) << 3)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 87 | } |
| 88 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 89 | /* IOTRAP(3) SMI function call */ |
| 90 | if (IOTRAP(3)) { |
| 91 | if (gnvs && gnvs->smif) |
| 92 | io_trap_handler(gnvs->smif); // call function smif |
| 93 | return; |
| 94 | } |
| 95 | |
| 96 | /* IOTRAP(2) currently unused |
| 97 | * IOTRAP(1) currently unused */ |
| 98 | |
| 99 | /* IOTRAP(0) SMIC */ |
| 100 | if (IOTRAP(0)) { |
| 101 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 102 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 103 | data = RCBA32(0x1e18); |
| 104 | data &= mask; |
| 105 | // if (smi1) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 106 | // southbridge_smi_command(data); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 107 | // return; |
| 108 | } |
| 109 | // Fall through to debug |
| 110 | } |
| 111 | |
| 112 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); |
Elyes HAOUAS | 70d79a4 | 2016-08-21 18:36:06 +0200 | [diff] [blame] | 113 | for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 114 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 115 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 116 | printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 117 | |
| 118 | if (!(trap_cycle & (1 << 24))) { |
| 119 | /* Write Cycle */ |
| 120 | data = RCBA32(0x1e18); |
| 121 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 122 | } |
| 123 | #undef IOTRAP |
| 124 | } |
| 125 | |
Angel Pons | 2fa7f07 | 2021-01-06 00:48:39 +0100 | [diff] [blame] | 126 | /* |
| 127 | * PCH BIOS Spec Rev 0.7.0, Section 13.5 |
| 128 | * Additional xHCI Controller Configurations Prior to Entering S3/S4 |
| 129 | */ |
| 130 | static void xhci_a0_suspend_smm_workaround(void) |
| 131 | { |
| 132 | /* Workaround only applies to Panther Point stepping A0 */ |
| 133 | if (pch_silicon_revision() != PCH_STEP_A0) |
| 134 | return; |
| 135 | |
| 136 | /* The BAR is 64-bit, account for it being above 4 GiB */ |
| 137 | if (pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0 + 4)) |
| 138 | return; |
| 139 | |
| 140 | /* PCH datasheet indicates that only the upper 16 bits are valid */ |
| 141 | uintptr_t xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & |
| 142 | ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 143 | |
| 144 | if (smm_points_to_smram((void *)xhci_bar, 64 * KiB)) |
| 145 | return; |
| 146 | |
| 147 | /* Step 1: Set power state to D0 */ |
| 148 | pci_and_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, ~(3 << 0)); |
| 149 | |
| 150 | /* Step 2 */ |
| 151 | pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 152 | |
| 153 | /* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */ |
| 154 | for (unsigned int port = 0; port < 4; port++) { |
Elyes Haouas | af776d8 | 2022-12-04 09:09:49 +0100 | [diff] [blame] | 155 | if (read32p((xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0)) |
Angel Pons | 2fa7f07 | 2021-01-06 00:48:39 +0100 | [diff] [blame] | 156 | pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2); |
| 157 | } |
| 158 | |
| 159 | /* Step 7 */ |
| 160 | pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); |
| 161 | |
| 162 | /* Step 8: Set power state to D3 */ |
| 163 | pci_or_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, 3 << 0); |
| 164 | } |
| 165 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 166 | void southbridge_smm_xhci_sleep(u8 slp_type) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 167 | { |
Angel Pons | 2fa7f07 | 2021-01-06 00:48:39 +0100 | [diff] [blame] | 168 | /* Only Panther Point has xHCI */ |
| 169 | if (pch_silicon_type() != PCH_TYPE_PPT) |
| 170 | return; |
| 171 | |
| 172 | /* Verify that RCBA is still valid */ |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 173 | if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE)) |
Angel Pons | 2fa7f07 | 2021-01-06 00:48:39 +0100 | [diff] [blame] | 174 | return; |
| 175 | |
| 176 | if (RCBA32(FD) & PCH_DISABLE_XHCI) |
| 177 | return; |
| 178 | |
| 179 | switch (slp_type) { |
| 180 | case ACPI_S3: |
| 181 | case ACPI_S4: |
| 182 | xhci_a0_suspend_smm_workaround(); |
| 183 | break; |
| 184 | |
| 185 | case ACPI_S5: |
| 186 | /* |
| 187 | * PCH BIOS Spec Rev 0.7.0, Section 13.5 |
| 188 | * Additional xHCI Controller Configurations Prior to Entering S5 |
| 189 | * |
| 190 | * For all steppings: |
| 191 | * Step 1: Set power state to D3 (bits 1:0) |
| 192 | * Step 2: Set PME# enable bit (bit 8) |
| 193 | */ |
| 194 | pci_or_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, 1 << 8 | 3 << 0); |
| 195 | break; |
| 196 | } |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 197 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 198 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 199 | void southbridge_finalize_all(void) |
| 200 | { |
| 201 | intel_me_finalize_smm(); |
| 202 | intel_pch_finalize_smm(); |
| 203 | intel_sandybridge_finalize_smm(); |
| 204 | intel_model_206ax_finalize_smm(); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 205 | } |