Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 2 | |
| 3 | /* Mem setup common file for different types of DDR present on SMDK5420 boards. |
| 4 | */ |
| 5 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 7 | #include <delay.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 8 | #include <soc/clk.h> |
| 9 | #include <soc/dmc.h> |
| 10 | #include <soc/setup.h> |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 11 | |
| 12 | #define ZQ_INIT_TIMEOUT 10000 |
| 13 | |
| 14 | int dmc_config_zq(struct mem_timings *mem, |
| 15 | struct exynos5_phy_control *phy0_ctrl, |
| 16 | struct exynos5_phy_control *phy1_ctrl) |
| 17 | { |
| 18 | unsigned long val = 0; |
| 19 | int i; |
| 20 | |
| 21 | /* |
| 22 | * ZQ Calibration: |
| 23 | * Select Driver Strength, |
| 24 | * long calibration for manual calibration |
| 25 | */ |
| 26 | val = PHY_CON16_RESET_VAL; |
| 27 | val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; |
| 28 | val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; |
| 29 | val |= ZQ_CLK_DIV_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 30 | write32(&phy0_ctrl->phy_con16, val); |
| 31 | write32(&phy1_ctrl->phy_con16, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 32 | |
| 33 | /* Disable termination */ |
| 34 | if (mem->zq_mode_noterm) |
| 35 | val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 36 | write32(&phy0_ctrl->phy_con16, val); |
| 37 | write32(&phy1_ctrl->phy_con16, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 38 | |
| 39 | /* ZQ_MANUAL_START: Enable */ |
| 40 | val |= ZQ_MANUAL_STR; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 41 | write32(&phy0_ctrl->phy_con16, val); |
| 42 | write32(&phy1_ctrl->phy_con16, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 43 | |
| 44 | /* ZQ_MANUAL_START: Disable */ |
| 45 | val &= ~ZQ_MANUAL_STR; |
| 46 | |
| 47 | /* |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 48 | * Since we are manually calibrating the ZQ values, |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 49 | * we are looping for the ZQ_init to complete. |
| 50 | */ |
| 51 | i = ZQ_INIT_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 52 | while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 53 | udelay(1); |
| 54 | i--; |
| 55 | } |
| 56 | if (!i) |
| 57 | return -1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 58 | write32(&phy0_ctrl->phy_con16, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 59 | |
| 60 | i = ZQ_INIT_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 61 | while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 62 | udelay(1); |
| 63 | i--; |
| 64 | } |
| 65 | if (!i) |
| 66 | return -1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 67 | write32(&phy1_ctrl->phy_con16, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) |
| 73 | { |
| 74 | unsigned long val; |
| 75 | |
| 76 | if (mode == DDR_MODE_DDR3) { |
| 77 | val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 78 | write32(&dmc->phycontrol0, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 79 | } |
| 80 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 81 | /* Update DLL Information: Force DLL Resynchronization */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 82 | val = read32(&dmc->phycontrol0); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 83 | val |= FP_RSYNC; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 84 | write32(&dmc->phycontrol0, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 85 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 86 | /* Reset Force DLL Resynchronization */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 87 | val = read32(&dmc->phycontrol0); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 88 | val &= ~FP_RSYNC; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 89 | write32(&dmc->phycontrol0, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) |
| 93 | { |
| 94 | int channel, chip; |
| 95 | |
| 96 | for (channel = 0; channel < mem->dmc_channels; channel++) { |
| 97 | unsigned long mask; |
| 98 | |
| 99 | mask = channel << DIRECT_CMD_CHANNEL_SHIFT; |
| 100 | for (chip = 0; chip < mem->chips_to_configure; chip++) { |
| 101 | int i; |
| 102 | |
| 103 | mask |= chip << DIRECT_CMD_CHIP_SHIFT; |
| 104 | |
| 105 | /* Sending NOP command */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 106 | write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * TODO(alim.akhtar@samsung.com): Do we need these |
| 110 | * delays? This one and the next were not there for |
| 111 | * DDR3. |
| 112 | */ |
| 113 | udelay(100); |
| 114 | |
| 115 | /* Sending EMRS/MRS commands */ |
| 116 | for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 117 | write32(&dmc->directcmd, |
| 118 | mem->direct_cmd_msr[i] | mask); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 119 | udelay(100); |
| 120 | } |
| 121 | |
| 122 | if (mem->send_zq_init) { |
| 123 | /* Sending ZQINIT command */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 124 | write32(&dmc->directcmd, |
| 125 | DIRECT_CMD_ZQINIT | mask); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 126 | /* |
| 127 | * FIXME: This was originally sdelay(10000) |
| 128 | * in the imported u-boot code. That may have |
| 129 | * been meant to be sdelay(0x10000) since that |
| 130 | * was used elsewhere in this function. Either |
| 131 | * way seems to work, though. |
| 132 | */ |
| 133 | udelay(12); |
| 134 | } |
| 135 | } |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) |
| 140 | { |
| 141 | int channel, chip; |
| 142 | |
| 143 | for (channel = 0; channel < mem->dmc_channels; channel++) { |
| 144 | unsigned long mask; |
| 145 | |
| 146 | mask = channel << DIRECT_CMD_CHANNEL_SHIFT; |
| 147 | for (chip = 0; chip < mem->chips_per_channel; chip++) { |
| 148 | mask |= chip << DIRECT_CMD_CHIP_SHIFT; |
| 149 | |
| 150 | /* PALL (all banks precharge) CMD */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 151 | write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 152 | udelay(100); |
| 153 | } |
| 154 | } |
| 155 | } |