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Angel Pons1ddb8942020-04-04 18:51:26 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Gabe Black607c0b62013-05-16 05:45:57 -07002
Gabe Blackee4bfbf2013-08-13 21:05:43 -07003#include <arch/cache.h>
Julius Werner80af4422014-10-20 13:18:56 -07004#include <bootblock_common.h>
5#include <soc/clk.h>
6#include <soc/wakeup.h>
7#include <soc/cpu.h>
Gabe Black607c0b62013-05-16 05:45:57 -07008
Gabe Blackee4bfbf2013-08-13 21:05:43 -07009/* convenient shorthand (in MB) */
Julius Wernerf0cd03c2013-09-19 20:15:45 -070010#define SRAM_START (EXYNOS5_SRAM_BASE >> 20)
Gabe Blackee4bfbf2013-08-13 21:05:43 -070011#define SRAM_SIZE 1
12#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */
13
Vadim Bendebury0b341b32014-04-23 11:09:44 -070014void bootblock_soc_init(void)
Gabe Black607c0b62013-05-16 05:45:57 -070015{
Gabe Black607c0b62013-05-16 05:45:57 -070016 if (get_wakeup_state() == WAKEUP_DIRECT) {
17 wakeup();
18 /* Never returns. */
19 }
20
Gabe Blackee4bfbf2013-08-13 21:05:43 -070021 /* set up dcache and MMU */
22 mmu_init();
Julius Wernerf0cd03c2013-09-19 20:15:45 -070023 mmu_disable_range(0, SRAM_START);
Gabe Blackee4bfbf2013-08-13 21:05:43 -070024 mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
25 mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
Gabe Blackee4bfbf2013-08-13 21:05:43 -070026 dcache_mmu_enable();
27
Gabe Black607c0b62013-05-16 05:45:57 -070028 /* For most ARM systems, we have to initialize firmware media source
29 * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
30 * already handled by iROM so there's no need to setup again.
31 */
Gabe Black607c0b62013-05-16 05:45:57 -070032}