Sen Chu | 122b45b | 2022-10-18 14:02:14 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <delay.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <soc/pll.h> |
| 7 | #include <soc/pll_common.h> |
| 8 | #include <soc/pmif.h> |
| 9 | #include <soc/pmif_clk_common.h> |
| 10 | #include <soc/pmif_sw.h> |
| 11 | |
| 12 | #define FREQ_METER_ABIST_AD_OSC_CK 35 |
| 13 | |
| 14 | #define SCP_CLK_SRC BIT(1) |
| 15 | #define SCP_CLK_CG BIT(2) |
| 16 | |
| 17 | #define ULPOSC1_RG_OSC_DIV BIT(18) |
| 18 | |
| 19 | #define ULPOSC1_CALI_HW_MODE (BIT(16) | BIT(17)) |
| 20 | #define ULPOSC1_ENABLE_SW_MODE (BIT(18) | BIT(19)) |
| 21 | |
| 22 | u32 pmif_get_ulposc_freq_mhz(u32 cali_val) |
| 23 | { |
| 24 | u32 result; |
| 25 | |
| 26 | clrsetbits32(&mtk_apmixed->ap_pll_con0, ULPOSC1_CALI_HW_MODE, ULPOSC1_ENABLE_SW_MODE); |
| 27 | clrbits32(&mtk_apmixed->ulposc_con0, cali_val); |
| 28 | |
| 29 | /* enable ulposc1 */ |
| 30 | setbits32(&mtk_scp_clk->scp_clk_en, SCP_CLK_SRC); |
| 31 | udelay(150); |
| 32 | setbits32(&mtk_scp_clk->scp_clk_en, SCP_CLK_CG); |
| 33 | |
| 34 | result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK); |
| 35 | |
| 36 | return result / 1000; |
| 37 | } |
| 38 | |
| 39 | int pmif_clk_init(void) |
| 40 | { |
| 41 | u32 ulposc; |
| 42 | |
| 43 | /* get hardware default value */ |
| 44 | ulposc = pmif_get_ulposc_freq_mhz(ULPOSC1_RG_OSC_DIV); |
| 45 | if (pmif_ulposc_check(ulposc, FREQ_250MHZ)) |
| 46 | die("ERROR: failed to meet ulposc frequency\n"); |
| 47 | |
| 48 | mt_pll_spmi_mux_select(); |
| 49 | |
| 50 | return 0; |
| 51 | } |