James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on MT8186 Functional Specification |
| 5 | * Chapter number: 3.7 |
| 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
| 9 | #include <console/console.h> |
| 10 | #include <delay.h> |
| 11 | #include <soc/mt6366.h> |
| 12 | #include <soc/pmic_wrap.h> |
Zhiyong Tao | a747770 | 2022-03-24 18:57:44 +0800 | [diff] [blame] | 13 | #include <soc/pmif.h> |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 14 | #include <soc/regulator.h> |
| 15 | #include <timer.h> |
| 16 | |
| 17 | static struct pmic_setting init_setting[] = { |
| 18 | {0x1E, 0xA, 0xA, 0}, |
| 19 | {0x22, 0x1F00, 0x1F00, 0}, |
| 20 | {0x2E, 0x1, 0x1, 0}, |
| 21 | {0x30, 0x1, 0x1, 0}, |
| 22 | {0x36, 0x8888, 0xFFFF, 0}, |
| 23 | {0x3A, 0x8888, 0xFFFF, 0}, |
| 24 | {0x3C, 0x8888, 0xFFFF, 0}, |
| 25 | {0x3E, 0x888, 0xFFF, 0}, |
| 26 | {0x94, 0x0, 0xFFFF, 0}, |
| 27 | {0x10C, 0x18, 0x18, 0}, |
| 28 | {0x112, 0x4, 0x4, 0}, |
| 29 | {0x118, 0x8, 0x8, 0}, |
| 30 | {0x12A, 0x100, 0x180, 0}, |
| 31 | {0x134, 0x80, 0x2890, 0}, |
| 32 | {0x14C, 0x20, 0x20, 0}, |
| 33 | {0x198, 0x0, 0x1FF, 0}, |
| 34 | {0x790, 0x280, 0x780, 0}, |
| 35 | {0x7AC, 0x0, 0x2000, 0}, |
| 36 | {0x98A, 0x1840, 0x1E40, 0}, |
| 37 | {0xA08, 0x1, 0x1, 0}, |
| 38 | {0xA24, 0x1E00, 0x1F00, 0}, |
| 39 | {0xA38, 0x0, 0x100, 0}, |
Sen Chu | 0e5f51e | 2023-03-08 15:51:51 +0800 | [diff] [blame] | 40 | {0xA3C, 0x81F2, 0x81F2, 0}, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 41 | {0xA44, 0xFFFF, 0xFFFF, 0}, |
| 42 | {0xA46, 0xFC00, 0xFC00, 0}, |
| 43 | {0xC8A, 0x4, 0xC, 0}, |
| 44 | {0xF8C, 0xAAA, 0xAAA, 0}, |
| 45 | {0x1188, 0x0, 0x8000, 0}, |
| 46 | {0x119E, 0x6000, 0x7000, 0}, |
| 47 | {0x11A2, 0x0, 0x3000, 0}, |
| 48 | {0x11B0, 0x4000, 0x4000, 0}, |
| 49 | {0x11B4, 0x0, 0x100, 0}, |
| 50 | {0x123A, 0x8040, 0x83FF, 0}, |
| 51 | {0x123E, 0x4, 0x4, 0}, |
| 52 | {0x1242, 0x1, 0x1, 0}, |
| 53 | {0x1260, 0x0, 0x154, 0}, |
| 54 | {0x1312, 0x8, 0x8, 0}, |
| 55 | {0x1334, 0x0, 0x100, 0}, |
| 56 | {0x138A, 0x10, 0x7F, 0}, |
| 57 | {0x138C, 0x15, 0x7F, 0}, |
| 58 | {0x138E, 0x1030, 0x3030, 0}, |
| 59 | {0x140A, 0x10, 0x7F, 0}, |
| 60 | {0x140C, 0x15, 0x7F, 0}, |
| 61 | {0x140E, 0x1030, 0x3030, 0}, |
| 62 | {0x148A, 0x10, 0x7F, 0}, |
| 63 | {0x148E, 0x1030, 0x3030, 0}, |
| 64 | {0x14A2, 0x20, 0x20, 0}, |
| 65 | {0x150A, 0x10, 0x7F, 0}, |
| 66 | {0x150E, 0x1030, 0x3030, 0}, |
| 67 | {0x158A, 0x8, 0x7F, 0}, |
| 68 | {0x158C, 0x90C, 0x7F7F, 0}, |
| 69 | {0x158E, 0x1030, 0x3030, 0}, |
| 70 | {0x159C, 0x8, 0xC, 0}, |
| 71 | {0x15A2, 0x20, 0x20, 0}, |
| 72 | {0x168A, 0x50, 0x7F, 0}, |
| 73 | {0x168C, 0x1964, 0x7F7F, 0}, |
| 74 | {0x168E, 0x2020, 0x3030, 0}, |
| 75 | {0x16A2, 0x20, 0x20, 0}, |
| 76 | {0x16AA, 0x50, 0x7F, 0}, |
| 77 | {0x170C, 0x1964, 0x7F7F, 0}, |
| 78 | {0x170E, 0x2020, 0x3030, 0}, |
| 79 | {0x172A, 0x44, 0x7F, 0}, |
| 80 | {0x178C, 0x202, 0x7F7F, 0}, |
| 81 | {0x178E, 0x70, 0x73, 0}, |
| 82 | {0x1790, 0xC, 0xC, 0}, |
| 83 | {0x1798, 0x2810, 0x3F3F, 0}, |
| 84 | {0x179A, 0x800, 0x3F00, 0}, |
| 85 | {0x179E, 0x1, 0x1, 0}, |
| 86 | {0x1808, 0x2000, 0x3000, 0}, |
| 87 | {0x180C, 0x60, 0x60, 0}, |
| 88 | {0x1814, 0x3FF0, 0x7FFF, 0}, |
| 89 | {0x1816, 0x3, 0x7, 0}, |
| 90 | {0x181A, 0x6081, 0xFFBF, 0}, |
| 91 | {0x181C, 0x503, 0x787, 0}, |
| 92 | {0x181E, 0xA462, 0xFFFF, 0}, |
| 93 | {0x1820, 0xA662, 0xFFFF, 0}, |
| 94 | {0x1824, 0xDB6, 0xFFF, 0}, |
| 95 | {0x1828, 0x160, 0x160, 0}, |
| 96 | {0x1830, 0x3FF0, 0x7FFF, 0}, |
| 97 | {0x1832, 0x3, 0x7, 0}, |
| 98 | {0x1836, 0x6081, 0xFFBF, 0}, |
| 99 | {0x1838, 0x503, 0x787, 0}, |
| 100 | {0x183A, 0xA262, 0xFFFF, 0}, |
| 101 | {0x183C, 0xA262, 0xFFFF, 0}, |
| 102 | {0x1840, 0xDB6, 0xFFF, 0}, |
| 103 | {0x1888, 0x420, 0xE7C, 0}, |
| 104 | {0x188A, 0x801, 0x3C07, 0}, |
| 105 | {0x188C, 0x1F, 0x3F, 0}, |
| 106 | {0x188E, 0x129A, 0xFFFF, 0}, |
| 107 | {0x1894, 0x58, 0x1F8, 0}, |
| 108 | {0x1896, 0x1C, 0x7C, 0}, |
| 109 | {0x1898, 0x1805, 0x3C07, 0}, |
| 110 | {0x189A, 0xF, 0xF, 0}, |
| 111 | {0x189C, 0x221A, 0xFFFF, 0}, |
| 112 | {0x18A0, 0x2E, 0x3F, 0}, |
| 113 | {0x18A2, 0x0, 0x40, 0}, |
| 114 | {0x18A4, 0x2C06, 0x3C07, 0}, |
| 115 | {0x18A6, 0xF, 0xF, 0}, |
| 116 | {0x18A8, 0x221A, 0xFFFF, 0}, |
| 117 | {0x18AC, 0x2E, 0x3F, 0}, |
| 118 | {0x18AE, 0x0, 0x40, 0}, |
| 119 | {0x18B0, 0x1805, 0x3C07, 0}, |
| 120 | {0x18B2, 0xF, 0xF, 0}, |
| 121 | {0x18B4, 0x221A, 0xFFFF, 0}, |
| 122 | {0x18B8, 0x2E, 0x3F, 0}, |
| 123 | {0x18BC, 0x50, 0x4F0, 0}, |
| 124 | {0x18BE, 0x3C, 0xFC, 0}, |
| 125 | {0x18C0, 0x0, 0x300, 0}, |
| 126 | {0x18C2, 0x8886, 0xFFFF, 0}, |
| 127 | {0x1A0E, 0x3, 0x3, 0}, |
| 128 | {0x1A10, 0x1, 0x1, 0}, |
| 129 | {0x1A12, 0x0, 0x1, 0}, |
| 130 | {0x1A14, 0x0, 0x1, 0}, |
| 131 | {0x1A16, 0x0, 0x1, 0}, |
| 132 | {0x1A18, 0x0, 0x1, 0}, |
| 133 | {0x1A1A, 0x0, 0x1, 0}, |
| 134 | {0x1A1C, 0x0, 0x1, 0}, |
| 135 | {0x1A1E, 0x0, 0x1, 0}, |
| 136 | {0x1A20, 0x0, 0x1, 0}, |
| 137 | {0x1A22, 0x0, 0x1, 0}, |
| 138 | {0x1A24, 0x0, 0x1, 0}, |
| 139 | {0x1A26, 0x0, 0x1, 0}, |
| 140 | {0x1A2C, 0x0, 0x1, 0}, |
| 141 | {0x1A2E, 0x0, 0x1, 0}, |
| 142 | {0x1A30, 0x0, 0x1, 0}, |
| 143 | {0x1A32, 0x0, 0x1, 0}, |
| 144 | {0x1A34, 0x0, 0x1, 0}, |
| 145 | {0x1A36, 0x0, 0x1, 0}, |
| 146 | {0x1A38, 0x0, 0x1, 0}, |
| 147 | {0x1A3A, 0x0, 0x1, 0}, |
| 148 | {0x1A3C, 0x0, 0x1, 0}, |
| 149 | {0x1A3E, 0x0, 0x1, 0}, |
| 150 | {0x1A40, 0x0, 0x1, 0}, |
| 151 | {0x1A42, 0x0, 0x1, 0}, |
| 152 | {0x1A44, 0x0, 0x1, 0}, |
| 153 | {0x1A46, 0x0, 0x1, 0}, |
| 154 | {0x1A48, 0x0, 0x1, 0}, |
| 155 | {0x1A4A, 0x0, 0x1, 0}, |
| 156 | {0x1A4C, 0x0, 0x1, 0}, |
| 157 | {0x1A4E, 0x0, 0x1, 0}, |
| 158 | {0x1A50, 0xE7FF, 0xE7FF, 0}, |
| 159 | {0x1A56, 0x7FFF, 0x7FFF, 0}, |
| 160 | {0x1B48, 0x10, 0x7F, 0}, |
| 161 | {0x1B4A, 0xF15, 0x7F7F, 0}, |
Sen Chu | a292f41 | 2022-09-05 19:19:48 +0800 | [diff] [blame] | 162 | /* Enable HW Tracking */ |
| 163 | {0x1B66, 0x10, 0x7F, 8}, |
| 164 | {0x1B68, 0x38, 0x7F, 0}, |
| 165 | {0x1B68, 0x63, 0x7F, 8}, |
| 166 | {0x1B64, 0x6, 0x7, 0}, |
| 167 | {0x1B6E, 0x10, 0x7F, 8}, |
| 168 | {0x1B70, 0x38, 0x7F, 0}, |
| 169 | {0x1B70, 0x63, 0x7F, 8}, |
| 170 | {0x1B6C, 0x6, 0x7, 0}, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 171 | {0x1B8A, 0x10, 0x7F, 0}, |
| 172 | {0x1B8C, 0xF15, 0x7F7F, 0}, |
| 173 | {0x1BA8, 0x10, 0x7F, 0}, |
| 174 | {0x1BAA, 0xF15, 0x7F7F, 0}, |
| 175 | {0x1BAC, 0x0, 0x3, 0}, |
| 176 | {0x1BCA, 0x10, 0x7F, 0}, |
| 177 | {0x1BCC, 0x70F, 0x7F7F, 0}, |
| 178 | {0x1C9E, 0x38, 0x7F, 0}, |
| 179 | {0x1CA0, 0x70F, 0x7F7F, 0}, |
Rex-BC Chen | 3a39202 | 2022-02-21 11:44:47 +0800 | [diff] [blame] | 180 | /* VSRAM_CORE: set SW mode */ |
| 181 | {0x1CA4, 0x1, 0xFFFF, 0}, |
| 182 | /* VSRAM_CORE: SW set OFF */ |
| 183 | {0x1C9C, 0x0, 0xFFFF, 0}, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 184 | {0x1EA2, 0x1B, 0x1F, 0}, |
| 185 | {0x1EA4, 0xC00, 0x1C00, 0}, |
| 186 | {0x1EA6, 0xC00, 0x1C00, 0}, |
| 187 | {0x1EA8, 0xC00, 0x1C00, 0}, |
| 188 | }; |
| 189 | |
| 190 | static struct pmic_setting lp_setting[] = { |
| 191 | /* Suspend */ |
| 192 | /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ |
| 193 | {0x1390, 0x1, 0x1, 0}, |
| 194 | /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ |
| 195 | {0x1490, 0x1, 0x1, 0}, |
| 196 | /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ |
| 197 | {0x1510, 0x1, 0x1, 0}, |
| 198 | /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ |
| 199 | {0x1590, 0x1, 0x1, 0}, |
| 200 | /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ |
| 201 | {0x1690, 0x1, 0x1, 0}, |
| 202 | /* [1:1]: RG_BUCK_VS2_HW0_OP_EN */ |
| 203 | {0x1710, 0x1, 0x1, 1}, |
| 204 | /* [1:1]: RG_BUCK_VS2_HW0_OP_CFG */ |
| 205 | {0x1716, 0x1, 0x1, 1}, |
| 206 | /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_EN */ |
| 207 | {0x1610, 0x1, 0x1, 1}, |
| 208 | /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_CFG */ |
| 209 | {0x1616, 0x1, 0x1, 1}, |
| 210 | /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ |
| 211 | {0x1410, 0x1, 0x1, 0}, |
| 212 | /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ |
| 213 | {0x1BD0, 0x1, 0x1, 0}, |
| 214 | /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_EN */ |
| 215 | {0x1BAE, 0x1, 0x1, 1}, |
| 216 | /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_CFG */ |
| 217 | {0x1BB4, 0x1, 0x1, 1}, |
| 218 | /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ |
| 219 | {0x1B4E, 0x1, 0x1, 0}, |
| 220 | /* [1:1]: RG_LDO_VXO22_HW0_OP_EN */ |
| 221 | {0x1A8A, 0x1, 0x1, 1}, |
| 222 | /* [1:1]: RG_LDO_VXO22_HW0_OP_CFG */ |
| 223 | {0x1A90, 0x1, 0x1, 1}, |
| 224 | /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ |
| 225 | {0x1C1E, 0x1, 0x1, 2}, |
| 226 | /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ |
| 227 | {0x1C24, 0x0, 0x1, 2}, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 228 | /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ |
| 229 | {0x1C46, 0x1, 0x1, 0}, |
| 230 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 231 | {0x1D1E, 0x1, 0x1, 0}, |
| 232 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 233 | {0x1D1E, 0x1, 0x1, 0}, |
| 234 | /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ |
| 235 | {0x1D8A, 0x1, 0x1, 0}, |
| 236 | /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ |
| 237 | {0x1C5A, 0x1, 0x1, 0}, |
| 238 | /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ |
| 239 | {0x1C6E, 0x1, 0x1, 0}, |
| 240 | /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ |
| 241 | {0x1C9E, 0x1, 0x1, 0}, |
| 242 | /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ |
| 243 | {0x1C8A, 0x1, 0x1, 0}, |
| 244 | /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ |
| 245 | {0x1B90, 0x1, 0x1, 0}, |
| 246 | /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ |
| 247 | {0x1CB2, 0x1, 0x1, 0}, |
| 248 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 249 | {0x1D34, 0x1, 0x1, 0}, |
| 250 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 251 | {0x1D34, 0x1, 0x1, 0}, |
| 252 | /* [1:1]: RG_LDO_VA12_HW0_OP_EN */ |
| 253 | {0x1A9E, 0x1, 0x1, 1}, |
| 254 | /* [1:1]: RG_LDO_VA12_HW0_OP_CFG */ |
| 255 | {0x1AA4, 0x1, 0x1, 1}, |
| 256 | /* [1:1]: RG_LDO_VAUX18_HW0_OP_EN */ |
| 257 | {0x1AB2, 0x1, 0x1, 1}, |
| 258 | /* [1:1]: RG_LDO_VAUX18_HW0_OP_CFG */ |
| 259 | {0x1AB8, 0x1, 0x1, 1}, |
| 260 | /* [1:1]: RG_LDO_VAUD28_HW0_OP_EN */ |
| 261 | {0x1AC6, 0x1, 0x1, 1}, |
| 262 | /* [1:1]: RG_LDO_VAUD28_HW0_OP_CFG */ |
| 263 | {0x1ACC, 0x1, 0x1, 1}, |
| 264 | /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ |
| 265 | {0x1ADA, 0x1, 0x1, 0}, |
| 266 | /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ |
| 267 | {0x1AEE, 0x1, 0x1, 0}, |
| 268 | /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ |
| 269 | {0x1C0A, 0x1, 0x1, 2}, |
| 270 | /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ |
| 271 | {0x1C10, 0x0, 0x1, 2}, |
| 272 | /* [1:1]: RG_LDO_VDRAM2_HW0_OP_EN */ |
| 273 | {0x1B0A, 0x1, 0x1, 1}, |
| 274 | /* [1:1]: RG_LDO_VDRAM2_HW0_OP_CFG */ |
| 275 | {0x1B10, 0x1, 0x1, 1}, |
| 276 | /* [0:0]: RG_LDO_VMC_SW_OP_EN */ |
| 277 | {0x1CC6, 0x1, 0x1, 0}, |
| 278 | /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ |
| 279 | {0x1CDA, 0x1, 0x1, 0}, |
| 280 | /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ |
| 281 | {0x1B1E, 0x1, 0x1, 0}, |
| 282 | /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ |
| 283 | {0x1D4A, 0x1, 0x1, 0}, |
| 284 | /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ |
| 285 | {0x1D5E, 0x1, 0x1, 0}, |
| 286 | /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ |
| 287 | {0x1D0A, 0x1, 0x1, 0}, |
| 288 | /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ |
| 289 | {0x1B32, 0x1, 0x1, 1}, |
| 290 | /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ |
| 291 | {0x1B38, 0x1, 0x1, 1}, |
| 292 | /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ |
| 293 | {0x1B32, 0x1, 0x1, 1}, |
| 294 | /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ |
| 295 | {0x1B38, 0x1, 0x1, 1}, |
| 296 | /* [1:1]: RG_LDO_VBIF28_HW0_OP_EN */ |
| 297 | {0x1DA0, 0x1, 0x1, 1}, |
| 298 | /* [1:1]: RG_LDO_VBIF28_HW0_OP_CFG */ |
| 299 | {0x1DA6, 0x0, 0x1, 1}, |
| 300 | |
| 301 | /* Deep idle setting */ |
| 302 | /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ |
| 303 | {0x1390, 0x1, 0x1, 0}, |
| 304 | /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ |
| 305 | {0x1490, 0x1, 0x1, 0}, |
| 306 | /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ |
| 307 | {0x1510, 0x1, 0x1, 0}, |
| 308 | /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ |
| 309 | {0x1590, 0x1, 0x1, 0}, |
| 310 | /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ |
| 311 | {0x1690, 0x1, 0x1, 0}, |
| 312 | /* [3:3]: RG_BUCK_VS2_HW2_OP_EN */ |
| 313 | {0x1710, 0x1, 0x1, 3}, |
| 314 | /* [3:3]: RG_BUCK_VS2_HW2_OP_CFG */ |
| 315 | {0x1716, 0x1, 0x1, 3}, |
| 316 | /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_EN */ |
| 317 | {0x1610, 0x1, 0x1, 3}, |
| 318 | /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_CFG */ |
| 319 | {0x1616, 0x1, 0x1, 3}, |
| 320 | /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ |
| 321 | {0x1410, 0x1, 0x1, 0}, |
| 322 | /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ |
| 323 | {0x1BD0, 0x1, 0x1, 0}, |
| 324 | /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_EN */ |
| 325 | {0x1BAE, 0x1, 0x1, 3}, |
| 326 | /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_CFG */ |
| 327 | {0x1BB4, 0x1, 0x1, 3}, |
| 328 | /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ |
| 329 | {0x1B4E, 0x1, 0x1, 0}, |
| 330 | /* [3:3]: RG_LDO_VXO22_HW2_OP_EN */ |
| 331 | {0x1A8A, 0x1, 0x1, 3}, |
| 332 | /* [3:3]: RG_LDO_VXO22_HW2_OP_CFG */ |
| 333 | {0x1A90, 0x1, 0x1, 3}, |
| 334 | /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ |
| 335 | {0x1C1E, 0x1, 0x1, 2}, |
| 336 | /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ |
| 337 | {0x1C24, 0x0, 0x1, 2}, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 338 | /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ |
| 339 | {0x1C46, 0x1, 0x1, 0}, |
| 340 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 341 | {0x1D1E, 0x1, 0x1, 0}, |
| 342 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 343 | {0x1D1E, 0x1, 0x1, 0}, |
| 344 | /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ |
| 345 | {0x1D8A, 0x1, 0x1, 0}, |
| 346 | /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ |
| 347 | {0x1C5A, 0x1, 0x1, 0}, |
| 348 | /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ |
| 349 | {0x1C6E, 0x1, 0x1, 0}, |
| 350 | /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ |
| 351 | {0x1C9E, 0x1, 0x1, 0}, |
| 352 | /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ |
| 353 | {0x1C8A, 0x1, 0x1, 0}, |
| 354 | /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ |
| 355 | {0x1B90, 0x1, 0x1, 0}, |
| 356 | /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ |
| 357 | {0x1CB2, 0x1, 0x1, 0}, |
| 358 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 359 | {0x1D34, 0x1, 0x1, 0}, |
| 360 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 361 | {0x1D34, 0x1, 0x1, 0}, |
| 362 | /* [3:3]: RG_LDO_VA12_HW2_OP_EN */ |
| 363 | {0x1A9E, 0x1, 0x1, 3}, |
| 364 | /* [3:3]: RG_LDO_VA12_HW2_OP_CFG */ |
| 365 | {0x1AA4, 0x1, 0x1, 3}, |
| 366 | /* [3:3]: RG_LDO_VAUX18_HW2_OP_EN */ |
| 367 | {0x1AB2, 0x1, 0x1, 3}, |
| 368 | /* [3:3]: RG_LDO_VAUX18_HW2_OP_CFG */ |
| 369 | {0x1AB8, 0x1, 0x1, 3}, |
| 370 | /* [0:0]: RG_LDO_VAUD28_SW_OP_EN */ |
| 371 | {0x1AC6, 0x1, 0x1, 0}, |
| 372 | /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ |
| 373 | {0x1ADA, 0x1, 0x1, 0}, |
| 374 | /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ |
| 375 | {0x1AEE, 0x1, 0x1, 0}, |
| 376 | /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ |
| 377 | {0x1C0A, 0x1, 0x1, 2}, |
| 378 | /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ |
| 379 | {0x1C10, 0x0, 0x1, 2}, |
| 380 | /* [3:3]: RG_LDO_VDRAM2_HW2_OP_EN */ |
| 381 | {0x1B0A, 0x1, 0x1, 3}, |
| 382 | /* [3:3]: RG_LDO_VDRAM2_HW2_OP_CFG */ |
| 383 | {0x1B10, 0x1, 0x1, 3}, |
| 384 | /* [0:0]: RG_LDO_VMC_SW_OP_EN */ |
| 385 | {0x1CC6, 0x1, 0x1, 0}, |
| 386 | /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ |
| 387 | {0x1CDA, 0x1, 0x1, 0}, |
| 388 | /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ |
| 389 | {0x1B1E, 0x1, 0x1, 0}, |
| 390 | /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ |
| 391 | {0x1D4A, 0x1, 0x1, 0}, |
| 392 | /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ |
| 393 | {0x1D5E, 0x1, 0x1, 0}, |
| 394 | /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ |
| 395 | {0x1D0A, 0x1, 0x1, 0}, |
| 396 | /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ |
| 397 | {0x1B32, 0x1, 0x1, 3}, |
| 398 | /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ |
| 399 | {0x1B38, 0x1, 0x1, 3}, |
| 400 | /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ |
| 401 | {0x1B32, 0x1, 0x1, 3}, |
| 402 | /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ |
| 403 | {0x1B38, 0x1, 0x1, 3}, |
| 404 | /* [3:3]: RG_LDO_VBIF28_HW2_OP_EN */ |
| 405 | {0x1DA0, 0x1, 0x1, 3}, |
| 406 | /* [3:3]: RG_LDO_VBIF28_HW2_OP_CFG */ |
| 407 | {0x1DA6, 0x0, 0x1, 3}, |
| 408 | }; |
| 409 | |
| 410 | static struct pmic_setting scp_setting[] = { |
| 411 | /* scp voltage initialization */ |
| 412 | /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */ |
| 413 | {0x14A6, 0x20, 0x7F, 0}, |
| 414 | /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */ |
| 415 | {0x14A6, 0x20, 0x7F, 8}, |
| 416 | /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */ |
| 417 | {0x14A4, 0x1, 0x1, 0}, |
| 418 | /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */ |
| 419 | {0x14A4, 0x0, 0x1, 1}, |
| 420 | /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */ |
| 421 | {0x1BC6, 0x40, 0x7F, 0}, |
| 422 | /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */ |
| 423 | {0x1BC6, 0x40, 0x7F, 8}, |
| 424 | /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */ |
| 425 | {0x1BC4, 0x1, 0x1, 0}, |
| 426 | /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */ |
| 427 | {0x1BC4, 0x0, 0x1, 1}, |
| 428 | /* [4:4]: RG_SRCVOLTEN_LP_EN */ |
| 429 | {0x134, 0x1, 0x1, 4}, |
| 430 | }; |
| 431 | |
| 432 | static const int vddq_votrim[] = { |
| 433 | 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, |
| 434 | 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, |
| 435 | }; |
| 436 | |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 437 | static void mt6366_protect_control(bool en_protect) |
| 438 | { |
| 439 | /* Write a magic number 0x9CA7 to disable protection */ |
| 440 | pwrap_write_field(PMIC_TOP_TMA_KEY, en_protect ? 0 : 0x9CA7, 0xFFFF, 0); |
| 441 | } |
| 442 | |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 443 | static u32 pmic_read_efuse(int i) |
| 444 | { |
| 445 | u32 efuse_data = 0; |
| 446 | |
| 447 | /* 1. Enable efuse ctrl engine clock */ |
| 448 | pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); |
| 449 | pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); |
| 450 | |
| 451 | /* 2. */ |
| 452 | pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); |
| 453 | |
| 454 | /* 3. Set row to read */ |
| 455 | pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); |
| 456 | |
| 457 | /* 4. Toggle RG_OTP_RD_TRIG */ |
| 458 | if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) |
| 459 | pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); |
| 460 | else |
| 461 | pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); |
| 462 | |
| 463 | /* 5. Polling RG_OTP_RD_BUSY = 0 */ |
| 464 | udelay(300); |
| 465 | while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) |
| 466 | ; |
| 467 | |
| 468 | /* 6. Read RG_OTP_DOUT_SW */ |
| 469 | udelay(100); |
| 470 | efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); |
| 471 | |
| 472 | /* 7. Disable efuse ctrl engine clock */ |
| 473 | pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); |
| 474 | pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); |
| 475 | |
| 476 | return efuse_data; |
| 477 | } |
| 478 | |
| 479 | static int pmic_get_efuse_votrim(void) |
| 480 | { |
| 481 | const u32 cali_efuse = pmic_read_efuse(106) & 0xF; |
| 482 | assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); |
| 483 | return vddq_votrim[cali_efuse]; |
| 484 | } |
| 485 | |
| 486 | static u32 pmic_get_vcore_vol(void) |
| 487 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 488 | u16 vol_reg; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 489 | |
| 490 | vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); |
| 491 | return 500000 + vol_reg * 6250; |
| 492 | } |
| 493 | |
| 494 | static void pmic_set_vcore_vol(u32 vcore_uv) |
| 495 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 496 | u16 vol_reg; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 497 | |
| 498 | assert(vcore_uv >= 500000); |
| 499 | assert(vcore_uv <= 1100000); |
| 500 | |
| 501 | vol_reg = (vcore_uv - 500000) / 6250; |
| 502 | |
| 503 | pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); |
| 504 | pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); |
| 505 | udelay(1); |
| 506 | } |
| 507 | |
Rex-BC Chen | e7c9b53 | 2021-11-17 16:55:20 +0800 | [diff] [blame] | 508 | static u32 pmic_get_vproc12_vol(void) |
| 509 | { |
| 510 | u16 vol_reg; |
| 511 | |
| 512 | vol_reg = pwrap_read_field(PMIC_VPROC12_DBG0, 0x7F, 0); |
| 513 | return 500000 + vol_reg * 6250; |
| 514 | } |
| 515 | |
| 516 | static void pmic_set_vproc12_vol(u32 v_uv) |
| 517 | { |
| 518 | u16 vol_reg; |
| 519 | |
| 520 | assert(v_uv >= 500000); |
| 521 | assert(v_uv <= 1293750); |
| 522 | |
| 523 | vol_reg = (v_uv - 500000) / 6250; |
| 524 | |
| 525 | pwrap_write_field(PMIC_VPROC12_OP_EN, 1, 0x7F, 0); |
| 526 | pwrap_write_field(PMIC_VPROC12_VOSEL, vol_reg, 0x7F, 0); |
| 527 | udelay(1); |
| 528 | } |
| 529 | |
| 530 | static u32 pmic_get_vsram_proc12_vol(void) |
| 531 | { |
| 532 | u16 vol_reg; |
| 533 | |
| 534 | vol_reg = pwrap_read_field(PMIC_VSRAM_PROC12_DBG0, 0x7F, 0); |
| 535 | return 500000 + vol_reg * 6250; |
| 536 | } |
| 537 | |
| 538 | static void pmic_set_vsram_proc12_vol(u32 v_uv) |
| 539 | { |
| 540 | u16 vol_reg; |
| 541 | |
| 542 | assert(v_uv >= 500000); |
| 543 | assert(v_uv <= 1293750); |
| 544 | |
| 545 | vol_reg = (v_uv - 500000) / 6250; |
| 546 | |
| 547 | pwrap_write_field(PMIC_VSRAM_PROC12_OP_EN, 1, 0x7F, 0); |
| 548 | pwrap_write_field(PMIC_VSRAM_PROC12_VOSEL, vol_reg, 0x7F, 0); |
| 549 | udelay(1); |
| 550 | } |
| 551 | |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 552 | static u32 pmic_get_vdram1_vol(void) |
| 553 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 554 | u16 vol_reg; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 555 | |
| 556 | vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); |
| 557 | return 500000 + vol_reg * 12500; |
| 558 | } |
| 559 | |
| 560 | static void pmic_set_vdram1_vol(u32 vdram_uv) |
| 561 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 562 | u16 vol_reg; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 563 | |
| 564 | assert(vdram_uv >= 500000); |
| 565 | assert(vdram_uv <= 1300000); |
| 566 | |
| 567 | vol_reg = (vdram_uv - 500000) / 12500; |
| 568 | |
| 569 | pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); |
| 570 | pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); |
| 571 | udelay(1); |
| 572 | } |
| 573 | |
| 574 | static u32 pmic_get_vddq_vol(void) |
| 575 | { |
| 576 | int efuse_votrim; |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 577 | u16 cali_trim; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 578 | |
| 579 | if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) |
| 580 | return 0; |
| 581 | |
| 582 | efuse_votrim = pmic_get_efuse_votrim(); |
| 583 | cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); |
| 584 | assert(cali_trim < ARRAY_SIZE(vddq_votrim)); |
| 585 | return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; |
| 586 | } |
| 587 | |
| 588 | static void pmic_set_vddq_vol(u32 vddq_uv) |
| 589 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 590 | int target_mv, dram2_ori_mv, cali_offset_uv; |
| 591 | u16 cali_trim; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 592 | |
| 593 | assert(vddq_uv >= 530000); |
| 594 | assert(vddq_uv <= 680000); |
| 595 | |
| 596 | /* Round down to multiple of 10 */ |
| 597 | target_mv = (vddq_uv / 1000) / 10 * 10; |
| 598 | |
| 599 | dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; |
| 600 | cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); |
| 601 | |
| 602 | if (cali_offset_uv >= 80000) |
| 603 | cali_trim = 8; |
| 604 | else if (cali_offset_uv <= -70000) |
| 605 | cali_trim = 7; |
| 606 | else { |
| 607 | cali_trim = 0; |
| 608 | while (cali_trim < ARRAY_SIZE(vddq_votrim) && |
| 609 | vddq_votrim[cali_trim] != cali_offset_uv) |
| 610 | ++cali_trim; |
| 611 | assert(cali_trim < ARRAY_SIZE(vddq_votrim)); |
| 612 | } |
| 613 | |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 614 | mt6366_protect_control(false); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 615 | pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 616 | mt6366_protect_control(true); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 617 | udelay(1); |
| 618 | } |
| 619 | |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 620 | static u32 pmic_get_vmch_vol(void) |
| 621 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 622 | u32 ret; |
| 623 | u16 vol_reg; |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 624 | |
| 625 | vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); |
| 626 | |
| 627 | switch (vol_reg) { |
| 628 | case 2: |
| 629 | ret = 2900000; |
| 630 | break; |
| 631 | case 3: |
| 632 | ret = 3000000; |
| 633 | break; |
| 634 | case 5: |
| 635 | ret = 3300000; |
| 636 | break; |
| 637 | default: |
| 638 | printk(BIOS_ERR, "ERROR[%s] VMCH read fail: %d\n", __func__, vol_reg); |
| 639 | ret = 0; |
| 640 | break; |
| 641 | } |
| 642 | return ret; |
| 643 | } |
| 644 | |
| 645 | static void pmic_set_vmch_vol(u32 vmch_uv) |
| 646 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 647 | u16 val = 0; |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 648 | |
| 649 | switch (vmch_uv) { |
| 650 | case 2900000: |
| 651 | val = 2; |
| 652 | break; |
| 653 | case 3000000: |
| 654 | val = 3; |
| 655 | break; |
| 656 | case 3300000: |
| 657 | val = 5; |
| 658 | break; |
| 659 | default: |
| 660 | die("ERROR[%s]: VMCH voltage %u is not support.\n", __func__, vmch_uv); |
| 661 | return; |
| 662 | } |
| 663 | |
| 664 | pwrap_write_field(PMIC_VMCH_ANA_CON0, val, 0x7, 8); |
| 665 | |
| 666 | /* Force SW to turn on */ |
| 667 | pwrap_write_field(PMIC_LDO_VMCH_OP_EN, 1, 0xFF, 0); |
| 668 | pwrap_write_field(PMIC_LDO_VMCH_CON0, 1, 0xFF, 0); |
| 669 | } |
| 670 | |
| 671 | static u32 pmic_get_vmc_vol(void) |
| 672 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 673 | u32 ret; |
| 674 | u16 vol_reg; |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 675 | |
| 676 | vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); |
| 677 | |
| 678 | switch (vol_reg) { |
| 679 | case 0x4: |
| 680 | ret = 1800000; |
| 681 | break; |
| 682 | case 0xA: |
| 683 | ret = 2900000; |
| 684 | break; |
| 685 | case 0xB: |
| 686 | ret = 3000000; |
| 687 | break; |
| 688 | case 0xD: |
| 689 | ret = 3300000; |
| 690 | break; |
| 691 | default: |
| 692 | printk(BIOS_ERR, "ERROR[%s] VMC read fail: %d\n", __func__, vol_reg); |
| 693 | ret = 0; |
| 694 | break; |
| 695 | } |
| 696 | return ret; |
| 697 | } |
| 698 | |
| 699 | static void pmic_set_vmc_vol(u32 vmc_uv) |
| 700 | { |
Rex-BC Chen | 4b6c2b8 | 2021-11-23 15:20:02 +0800 | [diff] [blame] | 701 | u16 val = 0; |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 702 | |
| 703 | switch (vmc_uv) { |
| 704 | case 1800000: |
| 705 | val = 0x4; |
| 706 | break; |
| 707 | case 2900000: |
| 708 | val = 0xA; |
| 709 | break; |
| 710 | case 3000000: |
| 711 | val = 0xB; |
| 712 | break; |
| 713 | case 3300000: |
| 714 | val = 0xD; |
| 715 | break; |
| 716 | default: |
| 717 | die("ERROR[%s]: VMC voltage %u is not support.\n", __func__, vmc_uv); |
| 718 | return; |
| 719 | } |
| 720 | |
| 721 | pwrap_write_field(PMIC_VMC_ANA_CON0, val, 0xF, 8); |
| 722 | |
| 723 | /* Force SW to turn on */ |
| 724 | pwrap_write_field(PMIC_LDO_VMC_OP_EN, 1, 0xFF, 0); |
| 725 | pwrap_write_field(PMIC_LDO_VMC_CON0, 1, 0xFF, 0); |
| 726 | } |
| 727 | |
Cong Yang | f9d72e3 | 2023-04-13 14:50:48 +0800 | [diff] [blame] | 728 | #define VRF12_VOLTAGE_UV 1200000 |
| 729 | |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 730 | static u32 pmic_get_vrf12_vol(void) |
| 731 | { |
| 732 | return (pwrap_read_field(PMIC_LDO_VRF12_CON0, 0x3, 0) & |
Cong Yang | f9d72e3 | 2023-04-13 14:50:48 +0800 | [diff] [blame] | 733 | pwrap_read_field(PMIC_LDO_VRF12_OP_EN, 0x3, 0)) ? VRF12_VOLTAGE_UV : 0; |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 734 | } |
| 735 | |
Cong Yang | f9d72e3 | 2023-04-13 14:50:48 +0800 | [diff] [blame] | 736 | static void pmic_set_vrf12_vol(u32 vrf12_uv) |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 737 | { |
Cong Yang | f9d72e3 | 2023-04-13 14:50:48 +0800 | [diff] [blame] | 738 | assert(vrf12_uv == VRF12_VOLTAGE_UV); |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 739 | pwrap_write_field(PMIC_LDO_VRF12_CON0, 1, 0x3, 0); |
| 740 | pwrap_write_field(PMIC_LDO_VRF12_OP_EN, 1, 0x3, 0); |
| 741 | } |
| 742 | |
| 743 | static u32 pmic_get_vcn33_vol(void) |
| 744 | { |
| 745 | u32 ret; |
| 746 | u16 vol_reg; |
| 747 | |
| 748 | vol_reg = pwrap_read_field(PMIC_VCN33_ANA_CON0, 0x3, 8); |
| 749 | |
| 750 | switch (vol_reg) { |
| 751 | case 0x1: |
| 752 | ret = 3300000; |
| 753 | break; |
| 754 | case 0x2: |
| 755 | ret = 3400000; |
| 756 | break; |
| 757 | case 0x3: |
| 758 | ret = 3500000; |
| 759 | break; |
| 760 | default: |
| 761 | printk(BIOS_ERR, "ERROR[%s] VCN33 read fail: %d\n", __func__, vol_reg); |
| 762 | ret = 0; |
| 763 | break; |
| 764 | } |
| 765 | return ret; |
| 766 | } |
| 767 | |
| 768 | static void pmic_set_vcn33_vol(u32 vcn33_uv) |
| 769 | { |
| 770 | u16 val = 0; |
| 771 | |
| 772 | switch (vcn33_uv) { |
| 773 | case 3300000: |
| 774 | val = 0x1; |
| 775 | break; |
| 776 | case 3400000: |
| 777 | val = 0x2; |
| 778 | break; |
| 779 | case 3500000: |
| 780 | val = 0x3; |
| 781 | break; |
| 782 | default: |
| 783 | die("ERROR[%s]: VCN33 voltage %u is not support.\n", __func__, vcn33_uv); |
| 784 | return; |
| 785 | } |
| 786 | |
| 787 | pwrap_write_field(PMIC_VCN33_ANA_CON0, val, 0x3, 8); |
| 788 | |
| 789 | /* Force SW to turn on */ |
| 790 | pwrap_write_field(PMIC_LDO_VCN33_CON0_0, 1, 0x1, 0); |
| 791 | } |
| 792 | |
Cong Yang | de7e014 | 2023-04-11 20:10:59 +0800 | [diff] [blame] | 793 | #define VIO18_VOLTAGE_UV 1800000 |
| 794 | |
| 795 | static u32 pmic_get_vio18_vol(void) |
| 796 | { |
| 797 | return pwrap_read_field(PMIC_LDO_VIO18_CON0, 0x1, 0) ? VIO18_VOLTAGE_UV : 0; |
| 798 | } |
| 799 | |
| 800 | static void pmic_set_vio18_vol(u32 vio18_uv) |
| 801 | { |
| 802 | assert(vio18_uv == VIO18_VOLTAGE_UV); |
| 803 | pwrap_write_field(PMIC_LDO_VIO18_CON0, 1, 0x1, 0); |
| 804 | } |
| 805 | |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 806 | static void pmic_wdt_set(void) |
| 807 | { |
| 808 | /* [5]=1, RG_WDTRSTB_DEB */ |
| 809 | pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); |
| 810 | /* [1]=0, RG_WDTRSTB_MODE */ |
| 811 | pwrap_write_field(PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); |
| 812 | /* [0]=1, RG_WDTRSTB_EN */ |
| 813 | pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); |
| 814 | } |
| 815 | |
| 816 | static void mt6366_init_setting(void) |
| 817 | { |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 818 | mt6366_protect_control(false); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 819 | for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) |
| 820 | pwrap_write_field( |
| 821 | init_setting[i].addr, init_setting[i].val, |
| 822 | init_setting[i].mask, init_setting[i].shift); |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 823 | mt6366_protect_control(true); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 824 | } |
| 825 | |
| 826 | static void wk_sleep_voltage_by_ddr(void) |
| 827 | { |
| 828 | if (pwrap_read_field(PMIC_VM_MODE, 0x3, 0) == 0x2) |
| 829 | pwrap_write_field(PMIC_VDRAM1_VOSEL_SLEEP, 0x3A, 0x7F, 0); |
| 830 | } |
| 831 | |
| 832 | static void wk_power_down_seq(void) |
| 833 | { |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 834 | mt6366_protect_control(false); |
zhiyong tao | c53a0aa | 2022-05-04 10:46:12 +0800 | [diff] [blame] | 835 | /* Set VPROC12 power-down time slot to 0xF to avoid 20ms delay */ |
| 836 | pwrap_write_field(PMIC_CPSDSA4, 0xF, 0x1F, 0); |
Rex-BC Chen | fb6d6a9 | 2022-01-25 18:57:40 +0800 | [diff] [blame] | 837 | mt6366_protect_control(true); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 838 | } |
| 839 | |
| 840 | static void mt6366_lp_setting(void) |
| 841 | { |
| 842 | for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) |
| 843 | pwrap_write_field( |
| 844 | lp_setting[i].addr, lp_setting[i].val, |
| 845 | lp_setting[i].mask, lp_setting[i].shift); |
| 846 | } |
| 847 | |
| 848 | static void pmic_check_hwcid(void) |
| 849 | { |
Rex-BC Chen | 69e3cab | 2022-03-14 14:37:44 +0800 | [diff] [blame] | 850 | printk(BIOS_INFO, "%s: ID = %#x\n", __func__, |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 851 | pwrap_read_field(0x8, 0xFFFF, 0)); |
| 852 | } |
| 853 | |
| 854 | void mt6366_set_power_hold(bool enable) |
| 855 | { |
| 856 | pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); |
| 857 | } |
| 858 | |
| 859 | void mt6366_init_scp_voltage(void) |
| 860 | { |
| 861 | for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++) |
| 862 | pwrap_write_field( |
| 863 | scp_setting[i].addr, scp_setting[i].val, |
| 864 | scp_setting[i].mask, scp_setting[i].shift); |
| 865 | } |
| 866 | |
| 867 | void mt6366_set_vsim2_cali_mv(u32 vsim2_mv) |
| 868 | { |
| 869 | u16 vsim2_reg, cali_mv; |
| 870 | |
| 871 | cali_mv = vsim2_mv % 100; |
| 872 | assert(cali_mv % 10 == 0); |
| 873 | |
| 874 | switch (vsim2_mv - cali_mv) { |
| 875 | case 1700: |
| 876 | vsim2_reg = 0x3; |
| 877 | break; |
| 878 | case 1800: |
| 879 | vsim2_reg = 0x4; |
| 880 | break; |
| 881 | case 2700: |
| 882 | vsim2_reg = 0x8; |
| 883 | break; |
| 884 | case 3000: |
| 885 | vsim2_reg = 0xb; |
| 886 | break; |
| 887 | case 3100: |
| 888 | vsim2_reg = 0xc; |
| 889 | break; |
| 890 | default: |
| 891 | printk(BIOS_ERR, "%s: voltage %d is not supported\n", __func__, vsim2_mv); |
| 892 | return; |
| 893 | }; |
| 894 | |
| 895 | /* [11:8]=0x8, RG_VSIM2_VOSEL */ |
| 896 | pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_reg, 0xF, 8); |
| 897 | |
| 898 | /* [3:0], RG_VSIM2_VOCAL */ |
| 899 | pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); |
| 900 | } |
| 901 | |
| 902 | void mt6366_set_voltage(enum mt6366_regulator_id id, u32 voltage_uv) |
| 903 | { |
| 904 | switch (id) { |
| 905 | case MT6366_VCORE: |
| 906 | pmic_set_vcore_vol(voltage_uv); |
| 907 | break; |
| 908 | case MT6366_VDRAM1: |
| 909 | pmic_set_vdram1_vol(voltage_uv); |
| 910 | break; |
| 911 | case MT6366_VDDQ: |
| 912 | pmic_set_vddq_vol(voltage_uv); |
| 913 | break; |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 914 | case MT6366_VMCH: |
| 915 | pmic_set_vmch_vol(voltage_uv); |
| 916 | break; |
| 917 | case MT6366_VMC: |
| 918 | pmic_set_vmc_vol(voltage_uv); |
| 919 | break; |
Rex-BC Chen | e7c9b53 | 2021-11-17 16:55:20 +0800 | [diff] [blame] | 920 | case MT6366_VPROC12: |
| 921 | pmic_set_vproc12_vol(voltage_uv); |
| 922 | break; |
| 923 | case MT6366_VSRAM_PROC12: |
| 924 | pmic_set_vsram_proc12_vol(voltage_uv); |
| 925 | break; |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 926 | case MT6366_VRF12: |
Cong Yang | f9d72e3 | 2023-04-13 14:50:48 +0800 | [diff] [blame] | 927 | pmic_set_vrf12_vol(voltage_uv); |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 928 | break; |
| 929 | case MT6366_VCN33: |
| 930 | pmic_set_vcn33_vol(voltage_uv); |
| 931 | break; |
Cong Yang | de7e014 | 2023-04-11 20:10:59 +0800 | [diff] [blame] | 932 | case MT6366_VIO18: |
| 933 | pmic_set_vio18_vol(voltage_uv); |
| 934 | break; |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 935 | default: |
| 936 | printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); |
| 937 | break; |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | u32 mt6366_get_voltage(enum mt6366_regulator_id id) |
| 942 | { |
| 943 | switch (id) { |
| 944 | case MT6366_VCORE: |
| 945 | return pmic_get_vcore_vol(); |
| 946 | case MT6366_VDRAM1: |
| 947 | return pmic_get_vdram1_vol(); |
| 948 | case MT6366_VDDQ: |
| 949 | return pmic_get_vddq_vol(); |
Rex-BC Chen | dc4c2b9 | 2021-10-28 17:17:14 +0800 | [diff] [blame] | 950 | case MT6366_VMCH: |
| 951 | return pmic_get_vmch_vol(); |
| 952 | case MT6366_VMC: |
| 953 | return pmic_get_vmc_vol(); |
Rex-BC Chen | e7c9b53 | 2021-11-17 16:55:20 +0800 | [diff] [blame] | 954 | case MT6366_VPROC12: |
| 955 | return pmic_get_vproc12_vol(); |
| 956 | case MT6366_VSRAM_PROC12: |
| 957 | return pmic_get_vsram_proc12_vol(); |
Rex-BC Chen | 0069f6a | 2021-12-28 13:07:06 +0800 | [diff] [blame] | 958 | case MT6366_VRF12: |
| 959 | return pmic_get_vrf12_vol(); |
| 960 | case MT6366_VCN33: |
| 961 | return pmic_get_vcn33_vol(); |
Cong Yang | de7e014 | 2023-04-11 20:10:59 +0800 | [diff] [blame] | 962 | case MT6366_VIO18: |
| 963 | return pmic_get_vio18_vol(); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 964 | default: |
| 965 | printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); |
| 966 | break; |
| 967 | } |
| 968 | return 0; |
| 969 | } |
| 970 | |
| 971 | void mt6366_init(void) |
| 972 | { |
| 973 | struct stopwatch voltage_settled; |
| 974 | |
| 975 | if (pwrap_init()) |
| 976 | die("ERROR - Failed to initialize pmic wrap!"); |
| 977 | |
| 978 | pmic_check_hwcid(); |
| 979 | mt6366_set_power_hold(true); |
| 980 | pmic_wdt_set(); |
| 981 | mt6366_init_setting(); |
| 982 | stopwatch_init_usecs_expire(&voltage_settled, 200); |
| 983 | wk_sleep_voltage_by_ddr(); |
| 984 | wk_power_down_seq(); |
| 985 | mt6366_lp_setting(); |
Zhiyong Tao | a747770 | 2022-03-24 18:57:44 +0800 | [diff] [blame] | 986 | pmif_spmi_set_lp_mode(); |
James Lo | 1e0765d | 2021-10-05 18:14:12 +0800 | [diff] [blame] | 987 | |
| 988 | while (!stopwatch_expired(&voltage_settled)) |
| 989 | /* wait for voltages to settle */; |
| 990 | } |