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review.coreboot.org / coreboot / bfb11bec3b3fec638adf864a9b9b2cff6671fed8 / . / src / soc / intel / xeon_sp / cpx / chip.h
blob: 321073b57ffd9e313f4949e821a26af9352eb9b3 [file] [log] [blame]
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]2
3#ifndef _SOC_CHIP_H_
4#define _SOC_CHIP_H_
5
Dinesh Gehlot6fecff22023-01-17 06:02:16 +0000[diff] [blame]6#include <gpio.h>
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]7#include <intelblocks/cfg.h>
Marc Jones31ed8852021-01-15 13:29:14 -0700[diff] [blame]8#include <soc/acpi.h>
Jonathan Zhang7919d612020-04-02 17:27:54 -0700[diff] [blame]9#include <soc/irq.h>
10#include <stdint.h>
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]11
Morgan Jangb29d16f2020-05-25 12:23:59 +0800[diff] [blame]12#define MAX_PCH_PCIE_PORT 20
13
14/**
15 UPD_PCH_PCIE_PORT:
16 ForceEnable - Enable/Disable PCH PCIe port
17 PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
18**/
19struct pch_pcie_port {
20 uint8_t ForceEnable;
21 uint8_t PortLinkSpeed;
22};
23
24/**
25 PCIe Link Speed Selection
26 **/
27typedef enum {
28 PcieAuto = 0,
29 PcieGen1,
30 PcieGen2,
31 PcieGen3
32} pcie_link_speed;
33
Tim Chu58e1e0a2020-12-28 00:08:53 -0800[diff] [blame]34/**
35 enum for DDR Frequency Limit
36 **/
37enum ddr_freq_limit {
38 DDR_AUTO = 0x0,
39 DDR_1333 = 0x5,
40 DDR_1600 = 0x7,
41 DDR_1866 = 0x9,
42 DDR_2133 = 0xb,
43 DDR_2400 = 0xd,
44 DDR_2666 = 0xf,
45 DDR_2933 = 0x11,
46 DDR_3200 = 0x13
47};
48
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]49struct soc_intel_xeon_sp_cpx_config {
50 /* Common struct containing soc config data required by common code */
51 struct soc_intel_common_config common_soc_config;
52
Morgan Jangb29d16f2020-05-25 12:23:59 +0800[diff] [blame]53 /* Struct for configuring PCH PCIe port */
54 struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT];
55
Jonathan Zhang7919d612020-04-02 17:27:54 -0700[diff] [blame]56 /**
57 * Interrupt Routing configuration
58 * If bit7 is 1, the interrupt is disabled.
59 */
60 uint8_t pirqa_routing;
61 uint8_t pirqb_routing;
62 uint8_t pirqc_routing;
63 uint8_t pirqd_routing;
64 uint8_t pirqe_routing;
65 uint8_t pirqf_routing;
66 uint8_t pirqg_routing;
67 uint8_t pirqh_routing;
68
69 /**
70 * Device Interrupt Routing configuration
71 * Interrupt Pin x Route.
72 * 0h = PIRQA#
73 * 1h = PIRQB#
74 * 2h = PIRQC#
75 * 3h = PIRQD#
76 * 4h = PIRQE#
77 * 5h = PIRQF#
78 * 6h = PIRQG#
79 * 7h = PIRQH#
80 */
81 uint16_t ir00_routing;
82 uint16_t ir01_routing;
83 uint16_t ir02_routing;
84 uint16_t ir03_routing;
85 uint16_t ir04_routing;
86
87 /**
88 * Device Interrupt Polarity Control
89 * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
90 * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
91 * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
92 * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
93 */
94 uint32_t ipc0;
95 uint32_t ipc1;
96 uint32_t ipc2;
97 uint32_t ipc3;
98
99 uint64_t turbo_ratio_limit;
100 uint64_t turbo_ratio_limit_cores;
101
102 uint32_t pstate_req_ratio;
103
Jonathan Zhangd2718c92020-07-17 17:35:12 -0700[diff] [blame]104 uint8_t vtd_support;
105 uint8_t x2apic;
106
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]107 /* Generic IO decode ranges */
108 uint32_t gen1_dec;
109 uint32_t gen2_dec;
110 uint32_t gen3_dec;
111 uint32_t gen4_dec;
Sumeet R Pawnikar360684b2020-06-18 15:56:11 +0530[diff] [blame]112
113 /* TCC activation offset */
114 uint32_t tcc_offset;
Marc Jones31ed8852021-01-15 13:29:14 -0700[diff] [blame]115
116 enum acpi_cstate_mode cstate_states;
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]117};
118
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]119typedef struct soc_intel_xeon_sp_cpx_config config_t;
120
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]121#endif