blob: 46c8e76d94868607b0fee36118340a717ff22108 [file] [log] [blame]
Martin Roth1a3de8e2022-10-06 15:57:21 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
Martin Roth20646cd2023-01-04 21:27:06 -07003/* TODO: Update for Phoenix */
Martin Roth1a3de8e2022-10-06 15:57:21 -06004
5#include <acpi/acpi.h>
6#include <amdblocks/apob_cache.h>
7#include <device/pci.h>
8#include <fsp/api.h>
9#include <program_loading.h>
10
11static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
12{
13 scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
14}
15
16void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
17{
18 FSP_S_CONFIG *scfg = &supd->FspsConfig;
19
20 fsp_assign_vbios_upds(scfg);
21
22 /*
23 * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
24 * before FSP-S was loaded, we would introduce contention onto the SPI bus and
25 * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
26 * no SPI operations, we can read the APOB while FSP-S executes.
27 */
28 start_apob_cache_read();
29 /*
30 * We enqueue the payload to be loaded after the APOB. This might cause a bit of
31 * bus contention when loading uCode and OPROMs, but since those calls happen at
32 * different points in the boot state machine it's a little harder to sequence all the
33 * async loading correctly. So in order to keep the complexity down, we enqueue the
34 * payload preload here. The end goal will be to add uCode and OPROM preloading
35 * before the payload so that the sequencing is correct.
36 *
37 * While FSP-S is executing, it's not currently possible to enqueue other transactions
38 * because FSP-S doesn't call `thread_yield()`. So the payload will start loading
39 * right after FSP-S completes.
40 */
41 if (!acpi_is_wakeup_s3())
42 payload_preload();
43}