Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Jan Samek | edda0f9 | 2023-04-27 10:39:27 +0200 | [diff] [blame] | 3 | #ifndef __CPU_INTEL_HASWELL_CHIP_H__ |
| 4 | #define __CPU_INTEL_HASWELL_CHIP_H__ |
| 5 | |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 6 | #include <stdbool.h> |
| 7 | #include <stdint.h> |
| 8 | |
| 9 | struct cpu_vr_config { |
| 10 | /* |
| 11 | * Minimum voltage for C6/C7 state: |
| 12 | * 0x67 = 1.6V (full swing) |
| 13 | * ... |
| 14 | * 0x79 = 1.7V |
| 15 | * ... |
| 16 | * 0x83 = 1.8V (no swing) |
| 17 | */ |
| 18 | uint8_t cpu_min_vid; |
| 19 | |
| 20 | /* |
| 21 | * Set slow VR ramp rate on C-state exit: |
| 22 | * 0 = Fast VR ramp rate / 2 |
| 23 | * 1 = Fast VR ramp rate / 4 |
| 24 | * 2 = Fast VR ramp rate / 8 |
| 25 | * 3 = Fast VR ramp rate / 16 |
| 26 | */ |
| 27 | uint8_t slow_ramp_rate_set; |
| 28 | |
| 29 | /* Enable slow VR ramp rate */ |
| 30 | bool slow_ramp_rate_enable; |
| 31 | }; |
| 32 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 33 | struct cpu_intel_haswell_config { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | int tcc_offset; /* TCC Activation Offset */ |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 35 | |
| 36 | struct cpu_vr_config vr_config; |
Angel Pons | 8e6f162 | 2020-10-29 00:18:11 +0100 | [diff] [blame] | 37 | |
| 38 | /* Enable S0iX support */ |
| 39 | bool s0ix_enable; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | }; |
Jan Samek | edda0f9 | 2023-04-27 10:39:27 +0200 | [diff] [blame] | 41 | |
| 42 | #endif /* __CPU_INTEL_HASWELL_CHIP_H__ */ |