Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/smp/mpspec.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <string.h> |
| 25 | #include <stdint.h> |
| 26 | |
| 27 | #include <cpu/amd/amdk8_sysconf.h> |
| 28 | |
| 29 | extern u8 bus_isa; |
| 30 | extern u8 bus_rs690[8]; |
| 31 | extern u8 bus_sb600[2]; |
| 32 | |
| 33 | extern u32 apicid_sb600; |
| 34 | |
| 35 | extern u32 bus_type[256]; |
| 36 | extern u32 sbdn_rs690; |
| 37 | extern u32 sbdn_sb600; |
| 38 | |
| 39 | static void *smp_write_config_table(void *v) |
| 40 | { |
| 41 | struct mp_config_table *mc; |
| 42 | int isa_bus; |
| 43 | |
| 44 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 45 | mptable_init(mc, LAPIC_ADDR); |
| 46 | smp_write_processors(mc); |
| 47 | |
| 48 | get_bus_conf(); |
| 49 | printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600); |
| 50 | |
| 51 | mptable_write_buses(mc, NULL, &isa_bus); |
| 52 | if (isa_bus != bus_isa) { |
| 53 | printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n"); |
| 54 | } |
| 55 | /* I/O APICs: APIC ID Version State Address */ |
| 56 | { |
| 57 | device_t dev; |
| 58 | |
| 59 | dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); |
| 60 | if (dev) { |
| 61 | struct resource *res; |
| 62 | res = find_resource(dev, 0x74); |
| 63 | smp_write_ioapic(mc, apicid_sb600, 0x20, res->base); |
| 64 | } |
| 65 | } |
| 66 | mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); |
| 67 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 68 | smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); |
| 69 | smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); |
| 70 | |
| 71 | /* Compute the checksums */ |
| 72 | mc->mpe_checksum = |
| 73 | smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 74 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 75 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", |
| 76 | mc, smp_next_mpe_entry(mc)); |
| 77 | return smp_next_mpe_entry(mc); |
| 78 | } |
| 79 | |
| 80 | static void fixup_virtual_wire(void *v) |
| 81 | { |
| 82 | struct intel_mp_floating *mf = v; |
| 83 | |
| 84 | mf->mpf_checksum = 0; |
| 85 | mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE; |
| 86 | mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); |
| 87 | } |
| 88 | |
| 89 | unsigned long write_smp_table(unsigned long addr) |
| 90 | { |
| 91 | void *v; |
| 92 | v = smp_write_floating_table(addr); |
| 93 | fixup_virtual_wire(v); |
| 94 | return (unsigned long)smp_write_config_table(v); |
| 95 | } |