Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2010 Siemens AG, Inc. |
| 6 | * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <delay.h> |
| 27 | #include <boot/tables.h> |
| 28 | #include <cpu/x86/msr.h> |
| 29 | #include <cpu/amd/mtrr.h> |
| 30 | #include <device/pci_def.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include <cpu/x86/lapic.h> |
| 33 | #include <southbridge/amd/sb600/sb600.h> |
| 34 | #include <southbridge/amd/rs690/chip.h> |
| 35 | #include <southbridge/amd/rs690/rs690.h> |
| 36 | #include <superio/ite/it8712f/it8712f.h> |
| 37 | #include "chip.h" |
| 38 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL |
| 39 | #include <x86emu/x86emu.h> |
| 40 | #endif |
| 41 | #include "int15_func.h" |
| 42 | |
| 43 | // ****LCD panel ID support: ***** |
| 44 | // Callback Sub-Function 00h - Get LCD Panel ID |
| 45 | #define PANEL_TABLE_ID_NO 0 // no LCD |
| 46 | #define PANEL_TABLE_ID1 1 // 1024x768_65MHz_Dual |
| 47 | #define PANEL_TABLE_ID2 2 // 920x1200_162MHz |
| 48 | #define PANEL_TABLE_ID3 3 // 600x1200_162MHz |
| 49 | #define PANEL_TABLE_ID4 4 // 1024x768_65MHz |
| 50 | #define PANEL_TABLE_ID5 5 // 1400x1050_108MHz |
| 51 | #define PANEL_TABLE_ID6 6 // 1680x1050_119MHz |
| 52 | #define PANEL_TABLE_ID7 7 // 2048x1536_164MHz |
| 53 | #define PANEL_TABLE_ID8 8 // 1280x1024_108MHz |
| 54 | #define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01 |
| 55 | |
| 56 | // Callback Sub-Function 05h Select Boot-up TV Standard |
| 57 | #define TV_MODE_00 0x00 /* NTSC */ |
| 58 | #define TV_MODE_01 0x01 /* PAL */ |
| 59 | #define TV_MODE_02 0x02 /* PALM */ |
| 60 | #define TV_MODE_03 0x03 /* PAL60 */ |
| 61 | #define TV_MODE_04 0x04 /* NTSCJ */ |
| 62 | #define TV_MODE_05 0x05 /* PALCN */ |
| 63 | #define TV_MODE_06 0x06 /* PALN */ |
| 64 | #define TV_MODE_09 0x09 /* SCART-RGB */ |
| 65 | #define TV_MODE_NO 0xff /* No TV Support */ |
| 66 | |
| 67 | #define PLX_VIDDID 0x861610b5 |
| 68 | |
| 69 | /* 7475 Common Registers */ |
| 70 | #define REG_DEVREV2 0x12 /* ADT7490 only */ |
| 71 | #define REG_VTT 0x1E /* ADT7490 only */ |
| 72 | #define REG_EXTEND3 0x1F /* ADT7490 only */ |
| 73 | #define REG_VOLTAGE_BASE 0x20 |
| 74 | #define REG_TEMP_BASE 0x25 |
| 75 | #define REG_TACH_BASE 0x28 |
| 76 | #define REG_PWM_BASE 0x30 |
| 77 | #define REG_PWM_MAX_BASE 0x38 |
| 78 | #define REG_DEVID 0x3D |
| 79 | #define REG_VENDID 0x3E |
| 80 | #define REG_DEVID2 0x3F |
| 81 | #define REG_STATUS1 0x41 |
| 82 | #define REG_STATUS2 0x42 |
| 83 | #define REG_VID 0x43 /* ADT7476 only */ |
| 84 | #define REG_VOLTAGE_MIN_BASE 0x44 |
| 85 | #define REG_VOLTAGE_MAX_BASE 0x45 |
| 86 | #define REG_TEMP_MIN_BASE 0x4E |
| 87 | #define REG_TEMP_MAX_BASE 0x4F |
| 88 | #define REG_TACH_MIN_BASE 0x54 |
| 89 | #define REG_PWM_CONFIG_BASE 0x5C |
| 90 | #define REG_TEMP_TRANGE_BASE 0x5F |
| 91 | #define REG_PWM_MIN_BASE 0x64 |
| 92 | #define REG_TEMP_TMIN_BASE 0x67 |
| 93 | #define REG_TEMP_THERM_BASE 0x6A |
| 94 | #define REG_REMOTE1_HYSTERSIS 0x6D |
| 95 | #define REG_REMOTE2_HYSTERSIS 0x6E |
| 96 | #define REG_TEMP_OFFSET_BASE 0x70 |
| 97 | #define REG_CONFIG2 0x73 |
| 98 | #define REG_EXTEND1 0x76 |
| 99 | #define REG_EXTEND2 0x77 |
| 100 | #define REG_CONFIG1 0x40 // ADT7475 |
| 101 | #define REG_CONFIG3 0x78 |
| 102 | #define REG_CONFIG5 0x7C |
| 103 | #define REG_CONFIG6 0x10 // ADT7475 |
| 104 | #define REG_CONFIG7 0x11 // ADT7475 |
| 105 | #define REG_CONFIG4 0x7D |
| 106 | #define REG_STATUS4 0x81 /* ADT7490 only */ |
| 107 | #define REG_VTT_MIN 0x84 /* ADT7490 only */ |
| 108 | #define REG_VTT_MAX 0x86 /* ADT7490 only */ |
| 109 | |
| 110 | #define VID_VIDSEL 0x80 /* ADT7476 only */ |
| 111 | |
| 112 | #define CONFIG2_ATTN 0x20 |
| 113 | #define CONFIG3_SMBALERT 0x01 |
| 114 | #define CONFIG3_THERM 0x02 |
| 115 | #define CONFIG4_PINFUNC 0x03 |
| 116 | #define CONFIG4_MAXDUTY 0x08 |
| 117 | #define CONFIG4_ATTN_IN10 0x30 |
| 118 | #define CONFIG4_ATTN_IN43 0xC0 |
| 119 | #define CONFIG5_TWOSCOMP 0x01 |
| 120 | #define CONFIG5_TEMPOFFSET 0x02 |
| 121 | #define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */ |
| 122 | #define REMOTE1 0 |
| 123 | #define LOCAL 1 |
| 124 | #define REMOTE2 2 |
| 125 | |
| 126 | /* ADT7475 Settings */ |
| 127 | #define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */ |
| 128 | #define ADT7475_TEMP_COUNT 3 |
| 129 | #define ADT7475_TACH_COUNT 4 |
| 130 | #define ADT7475_PWM_COUNT 3 |
| 131 | |
| 132 | /* Macros to easily index the registers */ |
| 133 | #define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2)) |
| 134 | #define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2)) |
| 135 | |
| 136 | #define PWM_REG(idx) (REG_PWM_BASE + (idx)) |
| 137 | #define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx)) |
| 138 | #define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx)) |
| 139 | #define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx)) |
| 140 | |
| 141 | #define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx)) |
| 142 | #define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2)) |
| 143 | #define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2)) |
| 144 | |
| 145 | #define TEMP_REG(idx) (REG_TEMP_BASE + (idx)) |
| 146 | #define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2)) |
| 147 | #define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2)) |
| 148 | #define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx)) |
| 149 | #define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx)) |
| 150 | #define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx)) |
| 151 | #define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx)) |
| 152 | |
| 153 | #define SMBUS_IO_BASE 0x1000 |
| 154 | #define ADT7475_ADDRESS 0x2E |
| 155 | |
| 156 | #define D_OPEN (1 << 6) |
| 157 | #define D_CLS (1 << 5) |
| 158 | #define D_LCK (1 << 4) |
| 159 | #define G_SMRAME (1 << 3) |
| 160 | #define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB |
| 161 | |
| 162 | extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); |
| 163 | extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); |
| 164 | |
| 165 | uint64_t uma_memory_base, uma_memory_size; |
| 166 | static u32 smbus_io_base = SMBUS_IO_BASE; |
| 167 | static u32 adt7475_address = ADT7475_ADDRESS; |
| 168 | |
| 169 | /* Macro to read the registers */ |
| 170 | #define adt7475_read_byte(reg) \ |
| 171 | do_smbus_read_byte(smbus_io_base, adt7475_address, reg) |
| 172 | |
| 173 | #define adt7475_write_byte(reg, val) \ |
| 174 | do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val) |
| 175 | |
| 176 | #define TWOS_COMPL 1 |
| 177 | |
| 178 | struct __table__{ |
| 179 | const char *info; |
| 180 | u8 val; |
| 181 | }; |
| 182 | |
| 183 | struct __table__ dutycycles[] = { |
| 184 | {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73}, |
| 185 | {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4}, |
| 186 | {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5}, |
| 187 | {"100%", 0xff} |
| 188 | }; |
| 189 | #define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__) |
| 190 | #define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix |
| 191 | #define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range" |
| 192 | #if TWOS_COMPL == 0 |
| 193 | struct __table__ temperatures[] = { |
| 194 | {"30°C", 0x5e},{"35°C", 0x63},{"40°C", 0x68},{"45°C", 0x6d},{"50°C", 0x72}, |
| 195 | {"55°C", 0x77},{"60°C", 0x7c},{"65°C", 0x81},{"70°C", 0x86},{"75°C", 0x8b}, |
| 196 | {"80°C", 0x90} |
| 197 | }; |
| 198 | #else |
| 199 | struct __table__ temperatures[] = { |
| 200 | {"30°C", 30},{"35°C", 35},{"40°C", 40},{"45°C", 45},{"50°C", 50}, |
| 201 | {"55°C", 55},{"60°C", 60},{"65°C", 65},{"70°C", 70},{"75°C", 75}, |
| 202 | {"80°C", 80} |
| 203 | }; |
| 204 | #endif |
| 205 | int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0}; |
| 206 | |
| 207 | #define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__) |
| 208 | #define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix |
| 209 | #define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range" |
| 210 | |
| 211 | struct fan_control { |
| 212 | unsigned int enable : 1; |
| 213 | u8 polarity; |
| 214 | u8 t_min; |
| 215 | u8 t_max; |
| 216 | u8 pwm_min; |
| 217 | u8 pwm_max; |
| 218 | u8 t_range; |
| 219 | }; |
| 220 | /* ############################################################################################# */ |
| 221 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL |
| 222 | static int int15_handler(void) |
| 223 | { |
| 224 | #define BOOT_DISPLAY_DEFAULT 0 |
| 225 | #define BOOT_DISPLAY_CRT (1 << 0) |
| 226 | #define BOOT_DISPLAY_TV (1 << 1) |
| 227 | #define BOOT_DISPLAY_EFP (1 << 2) |
| 228 | #define BOOT_DISPLAY_LCD (1 << 3) |
| 229 | #define BOOT_DISPLAY_CRT2 (1 << 4) |
| 230 | #define BOOT_DISPLAY_TV2 (1 << 5) |
| 231 | #define BOOT_DISPLAY_EFP2 (1 << 6) |
| 232 | #define BOOT_DISPLAY_LCD2 (1 << 7) |
| 233 | |
| 234 | printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", |
| 235 | __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); |
| 236 | |
| 237 | switch (M.x86.R_AX) { |
| 238 | case 0x4e08: /* Boot Display */ |
| 239 | switch (M.x86.R_BX) { |
| 240 | case 0x80: |
| 241 | M.x86.R_AX &= ~(0xff); // Success |
| 242 | M.x86.R_BX &= ~(0xff); |
| 243 | printk(BIOS_DEBUG, "Integrated System Information\n"); |
| 244 | break; |
| 245 | case 0x00: |
| 246 | M.x86.R_AX &= ~(0xff); |
| 247 | M.x86.R_BX = 0x00; |
| 248 | printk(BIOS_DEBUG, "Panel ID = 0\n"); |
| 249 | break; |
| 250 | case 0x05: |
| 251 | M.x86.R_AX &= ~(0xff); |
| 252 | M.x86.R_BX = 0xff; |
| 253 | printk(BIOS_DEBUG, "TV = off\n"); |
| 254 | break; |
| 255 | default: |
| 256 | return 0; |
| 257 | } |
| 258 | break; |
| 259 | case 0x5f35: /* Boot Display */ |
| 260 | M.x86.R_AX = 0x005f; // Success |
| 261 | M.x86.R_CL = BOOT_DISPLAY_DEFAULT; |
| 262 | break; |
| 263 | case 0x5f40: /* Boot Panel Type */ |
| 264 | // M.x86.R_AX = 0x015f; // Supported but failed |
| 265 | M.x86.R_AX = 0x005f; // Success |
| 266 | M.x86.R_CL = 3; // Display ID |
| 267 | break; |
| 268 | default: |
| 269 | /* Interrupt was not handled */ |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | /* Interrupt handled */ |
| 274 | return 1; |
| 275 | } |
| 276 | |
| 277 | static void int15_install(void) |
| 278 | { |
| 279 | typedef int (* yabel_handleIntFunc)(void); |
| 280 | extern yabel_handleIntFunc yabel_intFuncArray[256]; |
| 281 | yabel_intFuncArray[0x15] = int15_handler; |
| 282 | } |
| 283 | #endif |
| 284 | /* ############################################################################################# */ |
| 285 | |
| 286 | /** |
| 287 | * @brief |
| 288 | * |
| 289 | * @param |
| 290 | */ |
| 291 | |
| 292 | static u8 calc_trange(u8 t_min, u8 t_max) { |
| 293 | |
| 294 | u8 prev; |
| 295 | int i; |
| 296 | int diff = t_max - t_min; |
| 297 | |
| 298 | // walk through the trange table |
| 299 | for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) { |
| 300 | if( trange[i] < diff ) { |
| 301 | prev = i; // save last val |
| 302 | continue; |
| 303 | } |
| 304 | if( diff == trange[i] ) return i; |
| 305 | if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index |
| 306 | return i; |
| 307 | } |
| 308 | return prev; |
| 309 | } |
| 310 | |
| 311 | /******************************************************** |
| 312 | * sina uses SB600 GPIO9 to detect IDE_DMA66. |
| 313 | * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to |
| 314 | * get the cable type, 40 pin or 80 pin? |
| 315 | ********************************************************/ |
| 316 | static void cable_detect(void) |
| 317 | { |
| 318 | |
| 319 | u8 byte; |
| 320 | struct device *sm_dev; |
| 321 | struct device *ide_dev; |
| 322 | |
| 323 | /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */ |
| 324 | printk(BIOS_DEBUG, "%s.\n", __func__); |
| 325 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 326 | |
| 327 | byte = pci_read_config8(sm_dev, 0xA9); |
| 328 | byte |= (1 << 5); /* Set Gpio9 as input */ |
| 329 | pci_write_config8(sm_dev, 0xA9, byte); |
| 330 | |
| 331 | /* IDE Controller (Device 20, Function 1) on SB600 */ |
| 332 | ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); |
| 333 | |
| 334 | byte = pci_read_config8(ide_dev, 9); |
| 335 | printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility"); |
| 336 | |
| 337 | byte = pci_read_config8(ide_dev, 0x56); |
| 338 | byte &= ~(7 << 0); |
| 339 | if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) ) |
| 340 | byte |= 2 << 0; /* mode 2 */ |
| 341 | else |
| 342 | byte |= 5 << 0; /* mode 5 */ |
| 343 | printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0)); |
| 344 | pci_write_config8(ide_dev, 0x56, byte); |
| 345 | } |
| 346 | |
| 347 | /** |
| 348 | * @brief Detect the ADT7475 device |
| 349 | * |
| 350 | * @param |
| 351 | */ |
| 352 | |
| 353 | static const char * adt7475_detect( void ) { |
| 354 | |
| 355 | int vendid, devid, devid2; |
| 356 | const char *name = NULL; |
| 357 | |
| 358 | vendid = adt7475_read_byte(REG_VENDID); |
| 359 | devid2 = adt7475_read_byte(REG_DEVID2); |
| 360 | if (vendid != 0x41 || /* Analog Devices */ |
| 361 | (devid2 & 0xf8) != 0x68) { |
| 362 | return name; |
| 363 | } |
| 364 | |
| 365 | devid = adt7475_read_byte(REG_DEVID); |
| 366 | if (devid == 0x73) |
| 367 | name = "adt7473"; |
| 368 | else if (devid == 0x75 && adt7475_address == 0x2e) |
| 369 | name = "adt7475"; |
| 370 | else if (devid == 0x76) |
| 371 | name = "adt7476"; |
| 372 | else if ((devid2 & 0xfc) == 0x6c) |
| 373 | name = "adt7490"; |
| 374 | |
| 375 | return name; |
| 376 | } |
| 377 | |
| 378 | // thermal control defaults |
| 379 | const struct fan_control cpu_fan_control_defaults = { |
| 380 | .enable = 0, // disable by default |
| 381 | .polarity = 0, // high by default |
| 382 | .t_min = 3, // default = 45°C |
| 383 | .t_max = 7, // 65°C |
| 384 | .pwm_min = 1, // default dutycycle = 30% |
| 385 | .pwm_max = 13, // 90% |
| 386 | }; |
| 387 | const struct fan_control case_fan_control_defaults = { |
| 388 | .enable = 0, // disable by default |
| 389 | .polarity = 0, // high by default |
| 390 | .t_min = 2, // default = 40°C |
| 391 | .t_max = 8, // 70°C |
| 392 | .pwm_min = 0, // default dutycycle = 25% |
| 393 | .pwm_max = 13, // 90% |
| 394 | }; |
| 395 | |
| 396 | static void pm_init( void ) |
| 397 | { |
| 398 | u16 word; |
| 399 | u8 byte; |
| 400 | device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 401 | |
| 402 | /* set SB600 GPIO 64 to GPIO with pull-up */ |
| 403 | byte = pm2_ioread(0x42); |
| 404 | byte &= 0x3f; |
| 405 | pm2_iowrite(0x42, byte); |
| 406 | |
| 407 | /* set GPIO 64 to tristate */ |
| 408 | word = pci_read_config16(sm_dev, 0x56); |
| 409 | word |= 1 << 7; |
| 410 | pci_write_config16(sm_dev, 0x56, word); |
| 411 | |
| 412 | /* set GPIO 64 internal pull-up */ |
| 413 | byte = pm2_ioread(0xf0); |
| 414 | byte &= 0xee; |
| 415 | pm2_iowrite(0xf0, byte); |
| 416 | |
| 417 | /* set Talert to be active low */ |
| 418 | byte = pm_ioread(0x67); |
| 419 | byte &= ~(1 << 5); |
| 420 | pm_iowrite(0x67, byte); |
| 421 | |
| 422 | /* set Talert to generate ACPI event */ |
| 423 | byte = pm_ioread(0x3c); |
| 424 | byte &= 0xf3; |
| 425 | pm_iowrite(0x3c, byte); |
| 426 | |
| 427 | /* set GPM5 to not wake from s5 */ |
| 428 | byte = pm_ioread(0x77); |
| 429 | byte &= ~(1 << 5); |
| 430 | pm_iowrite(0x77, byte); |
| 431 | } |
| 432 | |
| 433 | /** |
| 434 | * @brief Setup thermal config on SINA Mainboard |
| 435 | * |
| 436 | * @param |
| 437 | */ |
| 438 | |
| 439 | static void set_thermal_config(void) |
| 440 | { |
| 441 | u8 byte, byte2; |
| 442 | u8 cpu_pwm_conf, case_pwm_conf; |
| 443 | device_t sm_dev; |
| 444 | struct fan_control cpu_fan_control, case_fan_control; |
| 445 | const char *name = NULL; |
| 446 | |
| 447 | |
| 448 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 449 | smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE |
| 450 | |
| 451 | if( (name = adt7475_detect()) == NULL ) { |
| 452 | printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address); |
| 453 | return; |
| 454 | } |
| 455 | printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address); |
| 456 | |
| 457 | cpu_fan_control = cpu_fan_control_defaults; |
| 458 | case_fan_control = case_fan_control_defaults; |
| 459 | |
| 460 | if( get_option(&byte, "cpu_fan_control") == -4 ) { |
| 461 | printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__); |
| 462 | } else { |
| 463 | // get all the options needed |
| 464 | if( get_option(&byte, "cpu_fan_control") == 0 ) |
| 465 | cpu_fan_control.enable = byte ? 1 : 0; |
| 466 | |
| 467 | get_option(&cpu_fan_control.polarity, "cpu_fan_polarity"); |
| 468 | get_option(&cpu_fan_control.t_min, "cpu_t_min"); |
| 469 | get_option(&cpu_fan_control.t_max, "cpu_t_max"); |
| 470 | get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min"); |
| 471 | get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max"); |
| 472 | |
| 473 | if( get_option(&byte, "chassis_fan_control") == 0) |
| 474 | case_fan_control.enable = byte ? 1 : 0; |
| 475 | get_option(&case_fan_control.polarity, "chassis_fan_polarity"); |
| 476 | get_option(&case_fan_control.t_min, "chassis_t_min"); |
| 477 | get_option(&case_fan_control.t_max, "chassis_t_max"); |
| 478 | get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min"); |
| 479 | get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max"); |
| 480 | |
| 481 | } |
| 482 | |
| 483 | printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable"); |
| 484 | printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high"); |
| 485 | |
| 486 | printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min)); |
| 487 | cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min); |
| 488 | |
| 489 | printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max)); |
| 490 | cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max); |
| 491 | |
| 492 | printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min)); |
| 493 | cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min); |
| 494 | |
| 495 | printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max)); |
| 496 | cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max); |
| 497 | |
| 498 | cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max); |
| 499 | printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range); |
| 500 | cpu_fan_control.t_range <<= 4; |
| 501 | cpu_fan_control.t_range |= (4 << 0); // 35.3Hz |
| 502 | |
| 503 | printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable"); |
| 504 | printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high"); |
| 505 | |
| 506 | printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min)); |
| 507 | case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min); |
| 508 | |
| 509 | printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max)); |
| 510 | case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max); |
| 511 | |
| 512 | printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min)); |
| 513 | case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min); |
| 514 | |
| 515 | printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max)); |
| 516 | case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max); |
| 517 | |
| 518 | case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max); |
| 519 | printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range); |
| 520 | case_fan_control.t_range <<= 4; |
| 521 | case_fan_control.t_range |= (4 << 0); // 35.3Hz |
| 522 | |
| 523 | cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output |
| 524 | case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output |
| 525 | cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5); // manual control |
| 526 | case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp |
| 527 | |
| 528 | /* set adt7475 */ |
| 529 | |
| 530 | adt7475_write_byte(REG_CONFIG1, 0x04); // clear register, bit 2 is read only |
| 531 | |
| 532 | /* Config Register 6: */ |
| 533 | adt7475_write_byte(REG_CONFIG6, 0x00); |
| 534 | /* Config Register 7 */ |
| 535 | adt7475_write_byte(REG_CONFIG7, 0x00); |
| 536 | |
| 537 | /* Config Register 5: */ |
| 538 | /* set Offset 64 format, enable THERM on Remote 1& Local */ |
| 539 | adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60); |
| 540 | /* No offset for remote 1 */ |
| 541 | adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00); |
| 542 | /* No offset for local */ |
| 543 | adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00); |
| 544 | /* No offset for remote 2 */ |
| 545 | adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00); |
| 546 | |
| 547 | /* remote 1 low temp limit */ |
| 548 | adt7475_write_byte(TEMP_MIN_REG(0), 0x00); |
| 549 | /* remote 1 High temp limit (90C) */ |
| 550 | adt7475_write_byte(TEMP_MAX_REG(0), 0x9a); |
| 551 | |
| 552 | /* local Low Temp Limit */ |
| 553 | adt7475_write_byte(TEMP_MIN_REG(1), 0x00); |
| 554 | /* local High Limit (90C) */ |
| 555 | adt7475_write_byte(TEMP_MAX_REG(1), 0x9a); |
| 556 | |
| 557 | /* remote 1 therm temp limit (95C) */ |
| 558 | adt7475_write_byte(TEMP_THERM_REG(0), 0x9f); |
| 559 | /* local therm temp limit (95C) */ |
| 560 | adt7475_write_byte(TEMP_THERM_REG(1), 0x9f); |
| 561 | |
| 562 | /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */ |
| 563 | adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf); |
| 564 | /* PWM 3 configuration register Case fan controlled by ADTxxxx temp */ |
| 565 | adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf); |
| 566 | |
| 567 | if( cpu_fan_control.enable ) { |
| 568 | /* PWM 1 minimum duty cycle (37%) */ |
| 569 | adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min); |
| 570 | /* PWM 1 Maximum duty cycle (100%) */ |
| 571 | adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max); |
| 572 | /* Remote 1 temperature Tmin (32C) */ |
| 573 | adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min); |
| 574 | /* remote 1 Trange (53C ramp range) */ |
| 575 | adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range); |
| 576 | } else { |
| 577 | adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max); |
| 578 | } |
| 579 | |
| 580 | if( case_fan_control.enable ) { |
| 581 | /* PWM 2 minimum duty cycle (37%) */ |
| 582 | adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min); |
| 583 | /* PWM 2 Maximum Duty Cycle (100%) */ |
| 584 | adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max); |
| 585 | /* local temperature Tmin (32C) */ |
| 586 | adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min); |
| 587 | /* local Trange (53C ramp range) */ |
| 588 | adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange |
| 589 | adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq |
| 590 | } else { |
| 591 | adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max); |
| 592 | } |
| 593 | |
| 594 | /* Config Register 3 - enable smbalert & therm */ |
| 595 | adt7475_write_byte(0x78, 0x03); |
| 596 | /* Config Register 4 - enable therm output */ |
| 597 | adt7475_write_byte(0x7d, 0x09); |
| 598 | /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */ |
| 599 | adt7475_write_byte(0x75, 0x2e); |
| 600 | |
| 601 | /* Config Register 1 Set Start bit */ |
| 602 | adt7475_write_byte(0x40, 0x05); |
| 603 | |
| 604 | /* Read status register to clear any old errors */ |
| 605 | byte2 = adt7475_read_byte(0x42); |
| 606 | byte = adt7475_read_byte(0x41); |
| 607 | |
| 608 | printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n", |
| 609 | byte2, byte); |
| 610 | |
| 611 | } |
| 612 | |
| 613 | /** |
| 614 | * @brief |
| 615 | * |
| 616 | * @param |
| 617 | */ |
| 618 | |
| 619 | static void patch_mmio_nonposted( void ) |
| 620 | { |
| 621 | unsigned reg, index; |
| 622 | resource_t rbase, rend; |
| 623 | u32 base, limit; |
| 624 | struct resource *resource; |
| 625 | device_t dev; |
| 626 | device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); |
| 627 | |
| 628 | printk(BIOS_DEBUG,"%s ...\n", __func__); |
| 629 | |
| 630 | dev = dev_find_slot(1, PCI_DEVFN(5,0)); |
| 631 | // the uma frame buffer |
| 632 | index = 0x10; |
| 633 | resource = probe_resource(dev, index); |
| 634 | if( resource ) { |
| 635 | // fixup resource nonposted in k8 mmio |
| 636 | /* Get the base address */ |
| 637 | rbase = (resource->base >> 8) & ~(0xff); |
| 638 | /* Get the limit (rounded up) */ |
| 639 | rend = (resource_end(resource) >> 8) & ~(0xff); |
| 640 | |
| 641 | printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend); |
| 642 | |
| 643 | for( reg = 0xb8; reg >= 0x80; reg -= 8 ) { |
| 644 | base = pci_read_config32(k8_f1,reg); |
| 645 | limit = pci_read_config32(k8_f1,reg+4); |
| 646 | printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit); |
| 647 | if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) { |
| 648 | limit |= (1 << 7); |
| 649 | printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit); |
| 650 | pci_write_config32(k8_f1, reg+4, limit); |
| 651 | break; |
| 652 | } |
| 653 | } |
| 654 | printk(BIOS_DEBUG, "\n"); |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | /** |
| 659 | * @brief |
| 660 | * |
| 661 | * @param |
| 662 | */ |
| 663 | |
| 664 | static void wait_pepp( void ) { |
| 665 | |
| 666 | int boot_delay = 0; |
| 667 | |
| 668 | if( get_option(&boot_delay, "boot_delay") < 0) |
| 669 | boot_delay = 5; |
| 670 | |
| 671 | printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay); |
| 672 | if ( boot_delay > 0 ) { |
| 673 | init_timer(); |
| 674 | // wait for PEPP-Board |
| 675 | printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay); |
| 676 | while ( boot_delay ) { |
| 677 | lapic_write(LAPIC_TMICT, 0xffffffff); |
| 678 | udelay(1000000); // delay time approx. 1 sec |
| 679 | printk(BIOS_INFO, "."); |
| 680 | boot_delay--; |
| 681 | } |
| 682 | printk(BIOS_INFO, "\n"); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | /** |
| 687 | * @brief |
| 688 | * |
| 689 | * @param |
| 690 | */ |
| 691 | |
| 692 | struct { |
| 693 | unsigned int bus; |
| 694 | unsigned int devfn; |
| 695 | } slot[] = { |
| 696 | {0, PCI_DEVFN(0,0)}, |
| 697 | {0, PCI_DEVFN(18,0)}, |
| 698 | {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)}, |
| 699 | {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)}, |
| 700 | {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)}, |
| 701 | {255,0}, |
| 702 | }; |
| 703 | |
| 704 | |
| 705 | static void update_subsystemid( device_t dev ) { |
| 706 | |
| 707 | int i; |
| 708 | struct mainboard_config *mb = dev->chip_info; |
| 709 | |
| 710 | dev->subsystem_vendor = 0x110a; |
| 711 | if( mb->plx_present ){ |
| 712 | dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077 |
| 713 | } else { |
| 714 | dev->subsystem_device = 0x4077; // U1P0 = 0x4077 |
| 715 | } |
| 716 | printk(BIOS_INFO, "%s [%x/%x]\n", dev->chip_ops->name, dev->subsystem_vendor, dev->subsystem_device ); |
| 717 | for( i=0; slot[i].bus < 255; i++) { |
| 718 | device_t d; |
| 719 | d = dev_find_slot(slot[i].bus,slot[i].devfn); |
| 720 | if( d ) { |
| 721 | printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); |
| 722 | d->subsystem_device = dev->subsystem_device; |
| 723 | } |
| 724 | } |
| 725 | } |
| 726 | |
| 727 | /** |
| 728 | * @brief |
| 729 | * |
| 730 | * @param |
| 731 | */ |
| 732 | |
| 733 | static void detect_hw_variant( device_t dev ) { |
| 734 | |
| 735 | device_t nb_dev =0, dev2 = 0; |
| 736 | struct southbridge_amd_rs690_config *cfg; |
| 737 | u32 lc_state, id = 0; |
| 738 | struct mainboard_config *mb = dev->chip_info; |
| 739 | |
| 740 | printk(BIOS_INFO, "Scan for PLX device ...\n"); |
| 741 | nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 742 | if (!nb_dev) { |
| 743 | die("CAN NOT FIND RS690 DEVICE, HALT!\n"); |
| 744 | /* NOT REACHED */ |
| 745 | } |
| 746 | |
| 747 | dev2 = dev_find_slot(0, PCI_DEVFN(2, 0)); |
| 748 | if (!dev2) { |
| 749 | die("CAN NOT FIND GFX DEVICE 2, HALT!\n"); |
| 750 | /* NOT REACHED */ |
| 751 | } |
| 752 | PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2 |
| 753 | |
| 754 | mdelay(40); |
| 755 | lc_state = nbpcie_p_read_index(dev2, 0xa5); /* lc_state */ |
| 756 | printk(BIOS_DEBUG, "lc current state=%x\n", lc_state); |
| 757 | /* LC_CURRENT_STATE = bit0-5 */ |
| 758 | switch( lc_state & 0x3f ){ |
| 759 | case 0x00: |
| 760 | case 0x01: |
| 761 | case 0x02: |
| 762 | case 0x03: |
| 763 | case 0x04: |
| 764 | printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n"); |
| 765 | break; |
| 766 | case 0x07: |
| 767 | case 0x10: |
| 768 | { |
| 769 | struct device dummy; |
| 770 | u32 pci_primary_bus, buses; |
| 771 | u16 secondary, subordinate; |
| 772 | |
| 773 | printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID)); |
| 774 | // save the existing primary/secondary/subordinate bus number configuration. |
| 775 | secondary = dev2->bus->secondary; |
| 776 | subordinate = dev2->bus->subordinate; |
| 777 | buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS); |
| 778 | |
| 779 | // Configure the bus numbers for this bridge |
| 780 | // bus number 1 is for internal gfx device, so we start with busnumber 2 |
| 781 | |
| 782 | buses &= 0xff000000; |
| 783 | buses |= ((2 << 8) | (0xff << 16)); |
| 784 | // setup the buses in device 2 |
| 785 | pci_write_config32(dev2,PCI_PRIMARY_BUS, buses); |
| 786 | |
| 787 | // fake a device descriptor for a device behind device 2 |
| 788 | dummy.bus = dev2->bus; |
| 789 | dummy.bus->secondary = (buses >> 8) & 0xff; |
| 790 | dummy.bus->subordinate = (buses >> 16) & 0xff; |
| 791 | dummy.path.type = DEVICE_PATH_PCI; |
| 792 | dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0 |
| 793 | |
| 794 | id = pci_read_config32(&dummy, PCI_VENDOR_ID); |
| 795 | /* Have we found something? |
| 796 | * Some broken boards return 0 if a slot is empty, but |
| 797 | * the expected answer is 0xffffffff |
| 798 | */ |
| 799 | if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { |
| 800 | printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id); |
| 801 | } else { |
| 802 | printk(BIOS_DEBUG, "found device [%x]\n", id); |
| 803 | } |
| 804 | // restore changes made for device 2 |
| 805 | dev2->bus->secondary = secondary; |
| 806 | dev2->bus->secondary = subordinate; |
| 807 | pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus); |
| 808 | } |
| 809 | break; |
| 810 | default: |
| 811 | break; |
| 812 | } |
| 813 | |
| 814 | mb->plx_present = 0; |
| 815 | if( id == PLX_VIDDID ){ |
| 816 | printk(BIOS_INFO, "found PLX device\n"); |
| 817 | mb->plx_present = 1; |
| 818 | cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info; |
| 819 | if( cfg->gfx_tmds ) { |
| 820 | printk(BIOS_INFO, "Disable 'gfx_tmds' support\n"); |
| 821 | cfg->gfx_tmds = 0; |
| 822 | cfg->gfx_link_width = 4; |
| 823 | } |
| 824 | return; |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | static void smm_lock( void ) |
| 829 | { |
| 830 | /* LOCK the SMM memory window and enable normal SMM. |
| 831 | * After running this function, only a full reset can |
| 832 | * make the SMM registers writable again. |
| 833 | */ |
| 834 | printk(BIOS_DEBUG, "Locking SMM.\n"); |
| 835 | pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69, |
| 836 | D_LCK | G_SMRAME | A_BASE_SEG); |
| 837 | } |
| 838 | |
| 839 | /** |
| 840 | * @brief Init |
| 841 | * |
| 842 | * @param the root device |
| 843 | */ |
| 844 | |
| 845 | static void init(device_t dev) |
| 846 | { |
| 847 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 |
| 848 | INT15_function_extensions int15_func; |
| 849 | #endif |
| 850 | |
| 851 | printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n", |
| 852 | dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); |
| 853 | |
| 854 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 |
| 855 | if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 ) |
| 856 | int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; |
| 857 | int15_func.regs.func05_TV_standard = TV_MODE_NO; |
| 858 | install_INT15_function_extensions(&int15_func); |
| 859 | #endif |
| 860 | set_thermal_config(); |
| 861 | pm_init(); |
| 862 | cable_detect(); |
| 863 | patch_mmio_nonposted(); |
| 864 | smm_lock(); |
| 865 | } |
| 866 | |
| 867 | /************************************************* |
| 868 | * enable the dedicated function in sina board. |
| 869 | * This function called early than rs690_enable. |
| 870 | *************************************************/ |
| 871 | static void enable_dev(device_t dev) |
| 872 | { |
| 873 | |
| 874 | printk(BIOS_INFO, "%s %s[%x/%x] %s\n", |
| 875 | dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); |
| 876 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL |
| 877 | /* Install custom int15 handler for VGA OPROM */ |
| 878 | int15_install(); |
| 879 | #endif |
| 880 | |
| 881 | detect_hw_variant(dev); |
| 882 | update_subsystemid(dev); |
| 883 | |
| 884 | #if (CONFIG_GFXUMA == 1) |
| 885 | { |
| 886 | msr_t msr, msr2; |
| 887 | |
| 888 | /* TOP_MEM: the top of DRAM below 4G */ |
| 889 | msr = rdmsr(TOP_MEM); |
| 890 | printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 891 | __func__, msr.lo, msr.hi); |
| 892 | |
| 893 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 894 | msr2 = rdmsr(TOP_MEM2); |
| 895 | |
| 896 | printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 897 | __func__, msr2.lo, msr2.hi); |
| 898 | |
| 899 | switch (msr.lo) { |
| 900 | case 0x10000000: /* 256M system memory */ |
| 901 | uma_memory_size = 0x2000000; /* 32M recommended UMA */ |
| 902 | break; |
| 903 | |
| 904 | case 0x18000000: /* 384M system memory */ |
| 905 | uma_memory_size = 0x4000000; /* 64M recommended UMA */ |
| 906 | break; |
| 907 | |
| 908 | case 0x20000000: /* 512M system memory */ |
| 909 | uma_memory_size = 0x4000000; /* 64M recommended UMA */ |
| 910 | break; |
| 911 | |
| 912 | default: /* 1GB and above system memory */ |
| 913 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 914 | break; |
| 915 | } |
| 916 | |
| 917 | uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ |
| 918 | |
| 919 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 920 | __func__, uma_memory_size, uma_memory_base); |
| 921 | |
| 922 | /* TODO: TOP_MEM2 */ |
| 923 | } |
| 924 | #else |
| 925 | uma_memory_size = 0; |
| 926 | uma_memory_base = 0; |
| 927 | #endif |
| 928 | |
| 929 | wait_pepp(); |
| 930 | dev->ops->init = init; // rest of mainboard init later |
| 931 | } |
| 932 | |
| 933 | /** |
| 934 | * @brief |
| 935 | * |
| 936 | * @param |
| 937 | */ |
| 938 | |
| 939 | int add_mainboard_resources(struct lb_memory *mem) |
| 940 | { |
| 941 | device_t dev; |
| 942 | struct resource *res; |
| 943 | |
| 944 | dev = dev_find_slot(0, PCI_DEVFN(0,0)); |
| 945 | res = probe_resource(dev, 0x1C); |
| 946 | if( res ) { |
| 947 | printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size); |
| 948 | lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); |
| 949 | } |
| 950 | /* UMA is removed from system memory in the northbridge code, but |
| 951 | * in some circumstances we want the memory mentioned as reserved. |
| 952 | */ |
| 953 | #if (CONFIG_GFXUMA == 1) |
| 954 | printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", |
| 955 | uma_memory_base, uma_memory_size); |
| 956 | lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); |
| 957 | #endif |
| 958 | return 0; |
| 959 | } |
| 960 | |
| 961 | struct chip_operations mainboard_ops = { |
| 962 | CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER) |
| 963 | .enable_dev = enable_dev, |
| 964 | }; |