| Martin Roth | 829c41d | 2014-05-21 14:21:22 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <delay.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include "soc.h" |
| 28 | |
| 29 | static int soc_revision_id = -1; |
| 30 | static int soc_type = -1; |
| 31 | |
| 32 | int soc_silicon_revision(void) |
| 33 | { |
| 34 | if (soc_revision_id < 0) |
| 35 | soc_revision_id = pci_read_config8( |
| 36 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 37 | PCI_REVISION_ID); |
| 38 | return soc_revision_id; |
| 39 | } |
| 40 | |
| 41 | int soc_silicon_type(void) |
| 42 | { |
| 43 | if (soc_type < 0) |
| 44 | soc_type = pci_read_config8( |
| 45 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 46 | PCI_DEVICE_ID + 1); |
| 47 | return soc_type; |
| 48 | } |
| 49 | |
| 50 | int soc_silicon_supported(int type, int rev) |
| 51 | { |
| 52 | int cur_type = soc_silicon_type(); |
| 53 | int cur_rev = soc_silicon_revision(); |
| 54 | |
| 55 | switch (type) { |
| 56 | case SOC_TYPE_RANGELEY: |
| 57 | if (cur_type == SOC_TYPE_RANGELEY && cur_rev >= rev) |
| 58 | return 1; |
| 59 | } |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | /* Set bit in Function Disble register to hide this device */ |
| 65 | static void soc_hide_devfn(unsigned devfn) |
| 66 | { |
| 67 | /* TODO Function Disable. */ |
| 68 | } |
| 69 | |
| 70 | |
| 71 | |
| 72 | |
| 73 | void soc_enable(device_t dev) |
| 74 | { |
| 75 | u32 reg32; |
| 76 | |
| 77 | if (!dev->enabled) { |
| 78 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 79 | |
| 80 | /* Ensure memory, io, and bus master are all disabled */ |
| 81 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 82 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 83 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 84 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 85 | |
| 86 | /* Hide this device if possible */ |
| 87 | soc_hide_devfn(dev->path.pci.devfn); |
| 88 | } else { |
| 89 | /* Enable SERR */ |
| 90 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 91 | reg32 |= PCI_COMMAND_SERR; |
| 92 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | struct chip_operations southbridge_intel_fsp_rangeley_ops = { |
| 97 | CHIP_NAME("Intel Rangeley Southbridge") |
| 98 | .enable_dev = soc_enable, |
| 99 | }; |