| Martin Roth | 829c41d | 2014-05-21 14:21:22 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/path.h> |
| 24 | #include <device/smbus.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <device/pci_ops.h> |
| 28 | #include <arch/io.h> |
| 29 | #include "soc.h" |
| 30 | #include "smbus.h" |
| 31 | |
| 32 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 33 | { |
| 34 | u16 device; |
| 35 | struct resource *res; |
| 36 | struct bus *pbus; |
| 37 | |
| 38 | device = dev->path.i2c.device; |
| 39 | pbus = get_pbus_smbus(dev); |
| 40 | res = find_resource(pbus->dev, 0x20); |
| 41 | |
| 42 | return do_smbus_read_byte(res->base, device, address); |
| 43 | } |
| 44 | |
| 45 | static struct smbus_bus_operations lops_smbus_bus = { |
| 46 | .read_byte = lsmbus_read_byte, |
| 47 | }; |
| 48 | |
| 49 | static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 50 | { |
| 51 | if (!vendor || !device) { |
| 52 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 53 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 54 | } else { |
| 55 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 56 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 57 | } |
| 58 | } |
| 59 | |
| 60 | static struct pci_operations smbus_pci_ops = { |
| 61 | .set_subsystem = smbus_set_subsystem, |
| 62 | }; |
| 63 | |
| 64 | static void rangeley_smbus_read_resources(device_t dev) |
| 65 | { |
| 66 | struct resource *res; |
| 67 | |
| 68 | /* |
| 69 | * The SMBus has two BARS. |
| 70 | * BAR0 - MMIO, not used at boot time |
| 71 | * BAR4 - IO, Used to talk to the SMBUS during boot, so we maintain |
| 72 | * the default setting in the resource allocator. |
| 73 | */ |
| 74 | |
| 75 | res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); |
| 76 | |
| 77 | res = new_resource(dev, PCI_BASE_ADDRESS_4); |
| 78 | res->base = SMBUS_IO_BASE; |
| 79 | res->size = 32; |
| 80 | res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | |
| 81 | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 82 | |
| 83 | } |
| 84 | |
| 85 | static struct device_operations smbus_ops = { |
| 86 | .read_resources = rangeley_smbus_read_resources, |
| 87 | .set_resources = pci_dev_set_resources, |
| 88 | .enable_resources = pci_dev_enable_resources, |
| 89 | .init = 0, |
| 90 | .scan_bus = scan_static_bus, |
| 91 | .ops_smbus_bus = &lops_smbus_bus, |
| 92 | .ops_pci = &smbus_pci_ops, |
| 93 | }; |
| 94 | |
| 95 | static const struct pci_driver rangeley_smbus __pci_driver = { |
| 96 | .ops = &smbus_ops, |
| 97 | .vendor = PCI_VENDOR_ID_INTEL, |
| 98 | .device = 0x1F3C, |
| 99 | }; |