| Martin Roth | 829c41d | 2014-05-21 14:21:22 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include "soc.h" |
| 26 | |
| 27 | #define SOC_EHCI1_TEMP_BAR0 0xe8000000 |
| 28 | |
| 29 | /* |
| 30 | * Setup USB controller MMIO BAR to prevent the |
| 31 | * reference code from resetting the controller. |
| 32 | * |
| 33 | * The BAR will be re-assigned during device |
| 34 | * enumeration so these are only temporary. |
| 35 | */ |
| 36 | void enable_usb_bar(void) |
| 37 | { |
| 38 | device_t usb0 = SOC_EHCI1_DEV; |
| 39 | u32 cmd; |
| 40 | |
| 41 | /* USB Controller 0 */ |
| 42 | pci_write_config32(usb0, PCI_BASE_ADDRESS_0, |
| 43 | SOC_EHCI1_TEMP_BAR0); |
| 44 | cmd = pci_read_config32(usb0, PCI_COMMAND); |
| 45 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 46 | pci_write_config32(usb0, PCI_COMMAND, cmd); |
| 47 | } |