| Martin Roth | 829c41d | 2014-05-21 14:21:22 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H |
| 22 | #define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H |
| 23 | |
| 24 | #include <arch/acpi.h> |
| 25 | |
| 26 | struct southbridge_intel_fsp_rangeley_config { |
| 27 | |
| 28 | /** |
| 29 | * GPI Routing configuration |
| 30 | * |
| 31 | * Only the lower two bits have a meaning: |
| 32 | * 00: No effect |
| 33 | * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 34 | * 10: SCI (if corresponding GPIO_EN bit is also set) |
| 35 | * 11: reserved |
| 36 | */ |
| 37 | uint8_t gpi0_routing; |
| 38 | uint8_t gpi1_routing; |
| 39 | uint8_t gpi2_routing; |
| 40 | uint8_t gpi3_routing; |
| 41 | uint8_t gpi4_routing; |
| 42 | uint8_t gpi5_routing; |
| 43 | uint8_t gpi6_routing; |
| 44 | uint8_t gpi7_routing; |
| 45 | uint8_t gpi8_routing; |
| 46 | uint8_t gpi9_routing; |
| 47 | uint8_t gpi10_routing; |
| 48 | uint8_t gpi11_routing; |
| 49 | uint8_t gpi12_routing; |
| 50 | uint8_t gpi13_routing; |
| 51 | uint8_t gpi14_routing; |
| 52 | uint8_t gpi15_routing; |
| 53 | |
| 54 | uint32_t gpe0_en; |
| 55 | uint16_t alt_gp_smi_en; |
| 56 | |
| 57 | /* IDE configuration */ |
| 58 | uint32_t ide_legacy_combined; |
| 59 | uint32_t sata_ahci; |
| 60 | uint8_t sata_port_map; |
| 61 | uint32_t sata_port0_gen3_tx; |
| 62 | uint32_t sata_port1_gen3_tx; |
| 63 | |
| 64 | uint32_t gen1_dec; |
| 65 | uint32_t gen2_dec; |
| 66 | uint32_t gen3_dec; |
| 67 | uint32_t gen4_dec; |
| 68 | |
| 69 | /* Enable linear PCIe Root Port function numbers starting at zero */ |
| 70 | uint8_t pcie_port_coalesce; |
| 71 | |
| 72 | /* Override PCIe ASPM */ |
| 73 | uint8_t pcie_aspm_f0; |
| 74 | uint8_t pcie_aspm_f1; |
| 75 | uint8_t pcie_aspm_f2; |
| 76 | uint8_t pcie_aspm_f3; |
| 77 | uint8_t pcie_aspm_f4; |
| 78 | uint8_t pcie_aspm_f5; |
| 79 | uint8_t pcie_aspm_f6; |
| 80 | uint8_t pcie_aspm_f7; |
| 81 | |
| 82 | /* ACPI configuration */ |
| 83 | uint8_t fadt_pm_profile; |
| 84 | uint16_t fadt_boot_arch; |
| 85 | |
| 86 | }; |
| 87 | |
| 88 | #endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */ |