blob: 19d615432066878b6383092e1dca4239d0e044bc [file] [log] [blame]
Martin Roth829c41d2014-05-21 14:21:22 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2014 Sage Electronic Engineering, LLC.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <string.h>
22#include <device/device.h>
23#include <device/pci.h>
24#include <arch/acpi.h>
25#include <southbridge/intel/fsp_rangeley/soc.h>
26#include <arch/io.h>
27
28#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
29#include <cpu/x86/smm.h>
30#endif
31
32/**
33 * Fill in the fadt with generic values that can be overridden later.
34 */
35
36typedef struct southbridge_intel_fsp_rangeley_config config_t;
37
38void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
39{
40 acpi_header_t *header = &(fadt->header);
41 struct device *lpcdev = dev_find_slot(SOC_LPC_DEVFN);
42 u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
43 config_t *config = lpcdev->chip_info;
44
45 memset((void *) fadt, 0, sizeof(acpi_fadt_t));
46
47 /*
48 * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
49 * in the ACPI 3.0b specification.
50 */
51
52 /* FADT Header Structure */
53 memcpy(header->signature, "FACP", 4);
54 header->length = sizeof(acpi_fadt_t);
55 header->revision = ACPI_FADT_REV_ACPI_3_0;
56 memcpy(header->oem_id, OEM_ID, 6);
57 memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
58 memcpy(header->asl_compiler_id, ASLC, 4);
59 header->asl_compiler_revision = 1;
60
61 /* ACPI Pointers */
62 fadt->firmware_ctrl = (unsigned long) facs;
63 fadt->dsdt = (unsigned long) dsdt;
64
65 fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
66 fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */
67
68 /* System Management */
69 fadt->sci_int = 0x09;
70 fadt->smi_cmd = 0x00; /* disable SMM */
71 fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */
72 fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */
73
74 /* Enable ACPI */
75 outl(inl(pmbase + PM1_CNT) | SCI_EN, pmbase + PM1_CNT);
76
77 /* Power Control */
78 fadt->s4bios_req = 0x00;
79 fadt->pstate_cnt = 0x00;
80
81 /* Control Registers - Base Address */
82 fadt->pm1a_evt_blk = pmbase + PM1_STS;
83 fadt->pm1b_evt_blk = 0x00; /* Not Used */
84 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
85 fadt->pm1b_cnt_blk = 0x00; /* Not Used */
86 fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
87 fadt->pm_tmr_blk = pmbase + PM1_TMR;
88 fadt->gpe0_blk = pmbase + GPE0_STS;
89 fadt->gpe1_blk = 0x00; /* Not Used */
90
91 /* Control Registers - Length */
92 fadt->pm1_evt_len = 4; /* 32 bits */
93 fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */
94 fadt->pm2_cnt_len = 1; /* 8 bits */
95 fadt->pm_tmr_len = 4; /* 32 bits */
96 fadt->gpe0_blk_len = 8; /* 64 bits */
97 fadt->gpe1_blk_len = 0;
98 fadt->gpe1_base = 0;
99 fadt->cst_cnt = 0;
100 fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
101 fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
102 fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
103 fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
104 fadt->duty_offset = 1;
105 fadt->duty_width = 0;
106
107 /* RTC Registers */
108 fadt->day_alrm = 0x0D;
109 fadt->mon_alrm = 0x00;
110 fadt->century = 0x00;
111 fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */
112
113 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
114 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
115 ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
116 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
117
118 /* Reset Register */
119 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
120 fadt->reset_reg.bit_width = 8;
121 fadt->reset_reg.bit_offset = 0;
122 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
123 fadt->reset_reg.addrl = 0xCF9;
124 fadt->reset_reg.addrh = 0x00;
125 fadt->reset_value = 6;
126
127 /* Reserved Bits */
128 fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */
129 fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */
130 fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */
131
132 /* Extended ACPI Pointers */
133 fadt->x_firmware_ctl_l = (unsigned long)facs;
134 fadt->x_firmware_ctl_h = 0x00;
135 fadt->x_dsdt_l = (unsigned long)dsdt;
136 fadt->x_dsdt_h = 0x00;
137
138 /* PM1 Status & PM1 Enable */
139 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
140 fadt->x_pm1a_evt_blk.bit_width = 32;
141 fadt->x_pm1a_evt_blk.bit_offset = 0;
142 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
143 fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
144 fadt->x_pm1a_evt_blk.addrh = 0x00;
145
146 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
147 fadt->x_pm1b_evt_blk.bit_width = 0;
148 fadt->x_pm1b_evt_blk.bit_offset = 0;
149 fadt->x_pm1b_evt_blk.access_size = 0;
150 fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
151 fadt->x_pm1b_evt_blk.addrh = 0x00;
152
153 /* PM1 Control Registers */
154 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
155 fadt->x_pm1a_cnt_blk.bit_width = 16;
156 fadt->x_pm1a_cnt_blk.bit_offset = 0;
157 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
158 fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
159 fadt->x_pm1a_cnt_blk.addrh = 0x00;
160
161 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
162 fadt->x_pm1b_cnt_blk.bit_width = 0;
163 fadt->x_pm1b_cnt_blk.bit_offset = 0;
164 fadt->x_pm1b_cnt_blk.access_size = 0;
165 fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
166 fadt->x_pm1b_cnt_blk.addrh = 0x00;
167
168 /* PM2 Control Registers */
169 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
170 fadt->x_pm2_cnt_blk.bit_width = 8;
171 fadt->x_pm2_cnt_blk.bit_offset = 0;
172 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
173 fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
174 fadt->x_pm2_cnt_blk.addrh = 0x00;
175
176 /* PM1 Timer Register */
177 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
178 fadt->x_pm_tmr_blk.bit_width = 32;
179 fadt->x_pm_tmr_blk.bit_offset = 0;
180 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
181 fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
182 fadt->x_pm_tmr_blk.addrh = 0x00;
183
184 /* General-Purpose Event Registers */
185 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
186 fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
187 fadt->x_gpe0_blk.bit_offset = 0;
188 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
189 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
190 fadt->x_gpe0_blk.addrh = 0x00;
191
192 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
193 fadt->x_gpe1_blk.bit_width = 0;
194 fadt->x_gpe1_blk.bit_offset = 0;
195 fadt->x_gpe1_blk.access_size = 0;
196 fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
197 fadt->x_gpe1_blk.addrh = 0x00;
198
199 header->checksum =
200 acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
201}