Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * (Written by Nico Huber <nico.huber@secunet.com> for secunet) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <console/console.h> |
| 24 | #include "gm45.h" |
| 25 | |
| 26 | #define CxRECy_MCHBAR(x, y) (0x14a0 + (x * 0x0100) + ((3 - y) * 4)) |
| 27 | #define CxRECy_SHIFT_L 0 |
| 28 | #define CxRECy_MASK_L (3 << CxRECy_SHIFT_L) |
| 29 | #define CxRECy_SHIFT_H 16 |
| 30 | #define CxRECy_MASK_H (3 << CxRECy_SHIFT_H) |
| 31 | #define CxRECy_T_SHIFT 28 |
| 32 | #define CxRECy_T_MASK (0xf << CxRECy_T_SHIFT) |
| 33 | #define CxRECy_T(t) ((t << CxRECy_T_SHIFT) & CxRECy_T_MASK) |
| 34 | #define CxRECy_P_SHIFT 24 |
| 35 | #define CxRECy_P_MASK (0x7 << CxRECy_P_SHIFT) |
| 36 | #define CxRECy_P(p) ((p << CxRECy_P_SHIFT) & CxRECy_P_MASK) |
| 37 | #define CxRECy_PH_SHIFT 22 |
| 38 | #define CxRECy_PH_MASK (0x3 << CxRECy_PH_SHIFT) |
| 39 | #define CxRECy_PH(p) ((p << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) |
| 40 | #define CxRECy_PM_SHIFT 20 |
| 41 | #define CxRECy_PM_MASK (0x3 << CxRECy_PM_SHIFT) |
| 42 | #define CxRECy_PM(p) ((p << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) |
| 43 | #define CxRECy_TIMING_MASK (CxRECy_T_MASK | CxRECy_P_MASK | \ |
| 44 | CxRECy_PH_MASK | CxRECy_PM_MASK) |
| 45 | |
| 46 | #define CxDRT3_C_SHIFT 7 |
| 47 | #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) |
| 48 | #define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) |
| 49 | /* group to byte-lane mapping: (cardF X group X 2 per group) */ |
| 50 | static const char bytelane_map[2][4][2] = { |
| 51 | /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, |
| 52 | /* F */{ { 0, 2 }, { 1, 3 }, { 4, 6 }, { 5, 7 } }, |
| 53 | }; |
| 54 | |
| 55 | #define PH_BOUND 4 |
| 56 | #define PH_STEP 2 |
| 57 | #define PM_BOUND 3 |
| 58 | #define C_BOUND 16 |
| 59 | typedef struct { |
| 60 | int c; |
| 61 | int pre; |
| 62 | int ph; |
| 63 | int t; |
| 64 | const int t_bound; |
| 65 | int p; |
| 66 | const int p_bound; |
| 67 | } rec_timing_t; |
| 68 | static void normalize_rec_timing(rec_timing_t *const timing) |
| 69 | { |
| 70 | while (timing->p >= timing->p_bound) { |
| 71 | timing->t++; |
| 72 | timing->p -= timing->p_bound; |
| 73 | } |
| 74 | while (timing->p < 0) { |
| 75 | timing->t--; |
| 76 | timing->p += timing->p_bound; |
| 77 | } |
| 78 | while (timing->t >= timing->t_bound) { |
| 79 | timing->ph += PH_STEP; |
| 80 | timing->t -= timing->t_bound; |
| 81 | } |
| 82 | while (timing->t < 0) { |
| 83 | timing->ph -= PH_STEP; |
| 84 | timing->t += timing->t_bound; |
| 85 | } |
| 86 | while (timing->ph >= PH_BOUND) { |
| 87 | timing->c++; |
| 88 | timing->ph -= PH_BOUND; |
| 89 | } |
| 90 | while (timing->ph < 0) { |
| 91 | timing->c--; |
| 92 | timing->ph += PH_BOUND; |
| 93 | } |
| 94 | if (timing->c < 0 || timing->c >= C_BOUND) |
| 95 | die("Timing under-/overflow during " |
| 96 | "receive-enable calibration.\n"); |
| 97 | } |
| 98 | |
| 99 | static void rec_full_backstep(rec_timing_t *const timing) |
| 100 | { |
| 101 | timing->c--; |
| 102 | } |
| 103 | static void rec_half_backstep(rec_timing_t *const timing) |
| 104 | { |
| 105 | timing->ph -= PH_STEP; |
| 106 | } |
| 107 | static void rec_quarter_step(rec_timing_t *const timing) |
| 108 | { |
| 109 | timing->t += (timing->t_bound) >> 1; |
| 110 | timing->p += (timing->t_bound & 1) * (timing->p_bound >> 1); |
| 111 | } |
| 112 | static void rec_quarter_backstep(rec_timing_t *const timing) |
| 113 | { |
| 114 | timing->t -= (timing->t_bound) >> 1; |
| 115 | timing->p -= (timing->t_bound & 1) * (timing->p_bound >> 1); |
| 116 | } |
| 117 | static void rec_smallest_step(rec_timing_t *const timing) |
| 118 | { |
| 119 | timing->p++; |
| 120 | } |
| 121 | |
| 122 | static void program_timing(int channel, int group, |
| 123 | rec_timing_t timings[][4]) |
| 124 | { |
| 125 | rec_timing_t *const timing = &timings[channel][group]; |
| 126 | |
| 127 | normalize_rec_timing(timing); |
| 128 | |
| 129 | /* C value is per channel. */ |
| 130 | unsigned int mchbar = CxDRT3_MCHBAR(channel); |
| 131 | MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | |
| 132 | CxDRT3_C(timing->c); |
| 133 | |
| 134 | /* All other per group. */ |
| 135 | mchbar = CxRECy_MCHBAR(channel, group); |
| 136 | u32 reg = MCHBAR32(mchbar); |
| 137 | reg &= ~CxRECy_TIMING_MASK; |
| 138 | reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | |
| 139 | CxRECy_PH(timing->ph) | CxRECy_PM(timing->pre); |
| 140 | MCHBAR32(mchbar) = reg; |
| 141 | } |
| 142 | |
| 143 | static int read_dqs_level(const int channel, const int lane) |
| 144 | { |
| 145 | unsigned int mchbar = 0x14f0 + (channel * 0x0100); |
| 146 | MCHBAR32(mchbar) &= ~(1 << 9); |
| 147 | MCHBAR32(mchbar) |= (1 << 9); |
| 148 | |
| 149 | /* Read from this channel. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 150 | read32((u32 *)raminit_get_rank_addr(channel, 0)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 151 | |
| 152 | mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); |
| 153 | return MCHBAR32(mchbar) & (1 << 30); |
| 154 | } |
| 155 | |
| 156 | static void find_dqs_low(const int channel, const int group, |
| 157 | rec_timing_t timings[][4], const char lane_map[][2]) |
| 158 | { |
| 159 | /* Look for DQS low, using quarter steps. */ |
| 160 | while (read_dqs_level(channel, lane_map[group][0]) || |
| 161 | read_dqs_level(channel, lane_map[group][1])) { |
| 162 | rec_quarter_step(&timings[channel][group]); |
| 163 | program_timing(channel, group, timings); |
| 164 | } |
| 165 | } |
| 166 | static void find_dqs_high(const int channel, const int group, |
| 167 | rec_timing_t timings[][4], const char lane_map[][2]) |
| 168 | { |
| 169 | /* Look for _any_ DQS high, using quarter steps. */ |
| 170 | while (!read_dqs_level(channel, lane_map[group][0]) && |
| 171 | !read_dqs_level(channel, lane_map[group][1])) { |
| 172 | rec_quarter_step(&timings[channel][group]); |
| 173 | program_timing(channel, group, timings); |
| 174 | } |
| 175 | } |
| 176 | static void find_dqs_edge_lowhigh(const int channel, const int group, |
| 177 | rec_timing_t timings[][4], |
| 178 | const char lane_map[][2]) |
| 179 | { |
| 180 | /* Advance beyond previous high to low transition. */ |
| 181 | timings[channel][group].t += 2; |
| 182 | program_timing(channel, group, timings); |
| 183 | |
| 184 | /* Coarsely look for DQS high. */ |
| 185 | find_dqs_high(channel, group, timings, lane_map); |
| 186 | |
| 187 | /* Go back and perform finer search. */ |
| 188 | rec_quarter_backstep(&timings[channel][group]); |
| 189 | program_timing(channel, group, timings); |
| 190 | while (!read_dqs_level(channel, lane_map[group][0]) || |
| 191 | !read_dqs_level(channel, lane_map[group][1])) { |
| 192 | rec_smallest_step(&timings[channel][group]); |
| 193 | program_timing(channel, group, timings); |
| 194 | } |
| 195 | } |
| 196 | static void find_preamble(const int channel, const int group, |
| 197 | rec_timing_t timings[][4], const char lane_map[][2]) |
| 198 | { |
| 199 | /* Look for DQS low, backstepping. */ |
| 200 | while (read_dqs_level(channel, lane_map[group][0]) || |
| 201 | read_dqs_level(channel, lane_map[group][1])) { |
| 202 | rec_full_backstep(&timings[channel][group]); |
| 203 | program_timing(channel, group, timings); |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | static void receive_enable_calibration(const timings_t *const timings, |
| 208 | const dimminfo_t *const dimms) |
| 209 | { |
| 210 | /* Override group to byte-lane mapping for raw card type F DIMMS. */ |
| 211 | static const char over_bytelane_map[2][4][2] = { |
| 212 | /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, |
| 213 | /* F */{ { 0, 0 }, { 3, 3 }, { 6, 6 }, { 5, 5 } }, |
| 214 | }; |
| 215 | |
| 216 | const int cardF[] = |
| 217 | { dimms[0].card_type == 0xf, dimms[0].card_type == 0xf }; |
| 218 | const unsigned t_bound = |
| 219 | (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; |
| 220 | const unsigned p_bound = |
| 221 | (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; |
| 222 | |
| 223 | rec_timing_t rec_timings[2][4] = { |
| 224 | { |
| 225 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 226 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 227 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 228 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound } |
| 229 | }, { |
| 230 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 231 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 232 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound }, |
| 233 | { timings->CAS + 1, 0, 0, 0, t_bound, 0, p_bound } |
| 234 | } |
| 235 | }; |
| 236 | |
| 237 | int ch, group; |
| 238 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 239 | const char (*const map)[2] = over_bytelane_map[cardF[ch]]; |
| 240 | for (group = 0; group < 4; ++group) { |
| 241 | program_timing(ch, group, rec_timings); |
| 242 | find_dqs_low(ch, group, rec_timings, map); |
| 243 | find_dqs_edge_lowhigh(ch, group, rec_timings, map); |
| 244 | |
| 245 | rec_quarter_step(&rec_timings[ch][group]); |
| 246 | program_timing(ch, group, rec_timings); |
| 247 | find_preamble(ch, group, rec_timings, map); |
| 248 | find_dqs_edge_lowhigh(ch, group, rec_timings, map); |
| 249 | rec_half_backstep(&rec_timings[ch][group]); |
| 250 | normalize_rec_timing(&rec_timings[ch][group]); |
| 251 | if (cardF[ch]) { |
| 252 | rec_timings[ch][group].t++; |
| 253 | program_timing(ch, group, rec_timings); |
| 254 | } |
| 255 | } |
| 256 | int c_min = C_BOUND; |
| 257 | for (group = 0; group < 4; ++group) { |
| 258 | if (rec_timings[ch][group].c < c_min) |
| 259 | c_min = rec_timings[ch][group].c; |
| 260 | } |
| 261 | for (group = 0; group < 4; ++group) { |
| 262 | rec_timings[ch][group].pre = |
| 263 | rec_timings[ch][group].c - c_min; |
| 264 | rec_timings[ch][group].c = c_min; |
| 265 | program_timing(ch, group, rec_timings); |
| 266 | printk(BIOS_SPEW, "Final timings for group %d " |
| 267 | "on channel %d: %d.%d.%d.%d.%d\n", |
| 268 | group, ch, |
| 269 | rec_timings[ch][group].c, |
| 270 | rec_timings[ch][group].pre, |
| 271 | rec_timings[ch][group].ph, |
| 272 | rec_timings[ch][group].t, |
| 273 | rec_timings[ch][group].p); |
| 274 | } |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | void raminit_receive_enable_calibration(const timings_t *const timings, |
| 279 | const dimminfo_t *const dimms) |
| 280 | { |
| 281 | int ch; |
| 282 | |
| 283 | /* Setup group to byte-lane mapping. */ |
| 284 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 285 | const char (*const map)[2] = |
| 286 | bytelane_map[dimms[ch].card_type == 0xf]; |
| 287 | unsigned int group; |
| 288 | for (group = 0; group < 4; ++group) { |
| 289 | const unsigned int mchbar = CxRECy_MCHBAR(ch, group); |
| 290 | u32 reg = MCHBAR32(mchbar); |
| 291 | reg &= ~((3 << 16) | (1 << 8) | 3); |
| 292 | reg |= (map[group][0] - group); |
| 293 | reg |= (map[group][1] - group - 1) << 16; |
| 294 | MCHBAR32(mchbar) = reg; |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | MCHBAR32(0x12a4) |= 1 << 31; |
| 299 | MCHBAR32(0x13a4) |= 1 << 31; |
| 300 | MCHBAR32(0x14f0) = (MCHBAR32(0x14f0) & ~(3 << 9)) | (1 << 9); |
| 301 | MCHBAR32(0x15f0) = (MCHBAR32(0x15f0) & ~(3 << 9)) | (1 << 9); |
| 302 | |
| 303 | receive_enable_calibration(timings, dimms); |
| 304 | |
| 305 | MCHBAR32(0x12a4) &= ~(1 << 31); |
| 306 | MCHBAR32(0x13a4) &= ~(1 << 31); |
| 307 | raminit_reset_readwrite_pointers(); |
| 308 | } |