Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Siemens AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <bootstate.h> |
Mario Scheithauer | 04ea73e | 2018-11-07 12:58:28 +0100 | [diff] [blame] | 17 | #include <cf9_reset.h> |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 18 | #include <console/console.h> |
Mario Scheithauer | d985cdc | 2018-11-07 08:50:45 +0100 | [diff] [blame] | 19 | #include <device/pci_def.h> |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 20 | #include <device/pci_ids.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <gpio.h> |
| 23 | #include <hwilib.h> |
| 24 | #include <intelblocks/lpc_lib.h> |
| 25 | #include <intelblocks/pcr.h> |
| 26 | #include <soc/pcr_ids.h> |
| 27 | #include <timer.h> |
| 28 | #include <timestamp.h> |
| 29 | #include <baseboard/variants.h> |
| 30 | |
| 31 | #define TX_DWORD3 0xa8c |
| 32 | |
| 33 | void variant_mainboard_final(void) |
| 34 | { |
| 35 | struct device *dev = NULL; |
Mario Scheithauer | d985cdc | 2018-11-07 08:50:45 +0100 | [diff] [blame] | 36 | uint16_t cmd = 0; |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 37 | |
Mario Scheithauer | 98689df | 2018-11-06 14:59:11 +0100 | [diff] [blame] | 38 | /* PIR6 register mapping for PCIe root ports |
| 39 | * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 40 | */ |
Mario Scheithauer | 98689df | 2018-11-06 14:59:11 +0100 | [diff] [blame] | 41 | pcr_write16(PID_ITSS, 0x314c, 0x2103); |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 42 | |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 43 | /* Enable CLKRUN_EN for power gating LPC */ |
| 44 | lpc_enable_pci_clk_cntl(); |
| 45 | |
| 46 | /* |
| 47 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 |
| 48 | * offset 0x341D bit3 and bit0. |
| 49 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 |
| 50 | * offset 0x341C bit [3:0]. |
| 51 | */ |
| 52 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
Mario Scheithauer | d985cdc | 2018-11-07 08:50:45 +0100 | [diff] [blame] | 53 | |
| 54 | /* Set Master Enable for on-board PCI device. */ |
| 55 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); |
| 56 | if (dev) { |
| 57 | cmd = pci_read_config16(dev, PCI_COMMAND); |
| 58 | cmd |= PCI_COMMAND_MASTER; |
| 59 | pci_write_config16(dev, PCI_COMMAND, cmd); |
Mario Scheithauer | 4946804 | 2018-11-08 13:49:24 +0100 | [diff] [blame] | 60 | |
| 61 | /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream |
| 62 | * XIO2001 PCIe to PCI Bridge. |
| 63 | */ |
| 64 | struct device *parent = dev->bus->dev; |
| 65 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
| 66 | pci_write_config8(parent, 0xd8, 0x1d); |
| 67 | } |
| 68 | |
| 69 | /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI |
| 70 | * Bridge on this mainboard. |
| 71 | */ |
| 72 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); |
| 73 | if (dev) { |
| 74 | struct device *parent = dev->bus->dev; |
| 75 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
| 76 | pci_write_config8(parent, 0xd8, 0x3c); |
Mario Scheithauer | d985cdc | 2018-11-07 08:50:45 +0100 | [diff] [blame] | 77 | } |
Mario Scheithauer | 04ea73e | 2018-11-07 12:58:28 +0100 | [diff] [blame] | 78 | |
| 79 | /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). |
| 80 | * When Bit 3 is set to 1 and then the reset button is pressed the PCH |
| 81 | * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard |
| 82 | * to generate the right reset timing. |
| 83 | */ |
| 84 | outb(FULL_RST, RST_CNT); |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void wait_for_legacy_dev(void *unused) |
| 88 | { |
| 89 | uint32_t legacy_delay, us_since_boot; |
| 90 | struct stopwatch sw; |
| 91 | |
| 92 | /* Open main hwinfo block. */ |
| 93 | if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) |
| 94 | return; |
| 95 | |
| 96 | /* Get legacy delay parameter from hwinfo. */ |
| 97 | if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, |
| 98 | sizeof(legacy_delay)) != sizeof(legacy_delay)) |
| 99 | return; |
| 100 | |
| 101 | us_since_boot = get_us_since_boot(); |
| 102 | /* No need to wait if the time since boot is already long enough.*/ |
| 103 | if (us_since_boot > legacy_delay) |
| 104 | return; |
| 105 | stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); |
| 106 | printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", |
| 107 | legacy_delay - us_since_boot, legacy_delay); |
| 108 | stopwatch_wait_until_expired(&sw); |
| 109 | printk(BIOS_NOTICE, "done!\n"); |
| 110 | } |
| 111 | |
| 112 | static void finalize_boot(void *unused) |
| 113 | { |
| 114 | /* Set coreboot ready LED. */ |
| 115 | gpio_output(CNV_RGI_DT, 1); |
| 116 | } |
| 117 | |
| 118 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); |
| 119 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |