| Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Siemens AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <bootstate.h> |
| 17 | #include <console/console.h> |
| 18 | #include <device/pci_ids.h> |
| 19 | #include <device/pci_ops.h> |
| 20 | #include <gpio.h> |
| 21 | #include <hwilib.h> |
| 22 | #include <intelblocks/lpc_lib.h> |
| 23 | #include <intelblocks/pcr.h> |
| 24 | #include <soc/pcr_ids.h> |
| 25 | #include <timer.h> |
| 26 | #include <timestamp.h> |
| 27 | #include <baseboard/variants.h> |
| 28 | |
| 29 | #define TX_DWORD3 0xa8c |
| 30 | |
| 31 | void variant_mainboard_final(void) |
| 32 | { |
| 33 | struct device *dev = NULL; |
| 34 | |
| 35 | /* |
| 36 | * PIR6 register mapping for PCIe root ports |
| 37 | * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# |
| 38 | */ |
| 39 | pcr_write16(PID_ITSS, 0x314c, 0x0321); |
| 40 | |
| 41 | /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ |
| 42 | dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); |
| 43 | if (dev) |
| 44 | pci_write_config8(dev, 0xd8, 0x3e); |
| 45 | |
| 46 | /* Enable CLKRUN_EN for power gating LPC */ |
| 47 | lpc_enable_pci_clk_cntl(); |
| 48 | |
| 49 | /* |
| 50 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 |
| 51 | * offset 0x341D bit3 and bit0. |
| 52 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 |
| 53 | * offset 0x341C bit [3:0]. |
| 54 | */ |
| 55 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
| 56 | |
| 57 | /* |
| 58 | * Correct the SATA transmit signal via the High Speed I/O Transmit |
| 59 | * Control Register 3. |
| 60 | * Bit [23:16] set the output voltage swing for TX line. |
| 61 | * The value 0x4a sets the swing level to 0.58 V. |
| 62 | */ |
| 63 | pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); |
| 64 | } |
| 65 | |
| 66 | static void wait_for_legacy_dev(void *unused) |
| 67 | { |
| 68 | uint32_t legacy_delay, us_since_boot; |
| 69 | struct stopwatch sw; |
| 70 | |
| 71 | /* Open main hwinfo block. */ |
| 72 | if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) |
| 73 | return; |
| 74 | |
| 75 | /* Get legacy delay parameter from hwinfo. */ |
| 76 | if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, |
| 77 | sizeof(legacy_delay)) != sizeof(legacy_delay)) |
| 78 | return; |
| 79 | |
| 80 | us_since_boot = get_us_since_boot(); |
| 81 | /* No need to wait if the time since boot is already long enough.*/ |
| 82 | if (us_since_boot > legacy_delay) |
| 83 | return; |
| 84 | stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); |
| 85 | printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", |
| 86 | legacy_delay - us_since_boot, legacy_delay); |
| 87 | stopwatch_wait_until_expired(&sw); |
| 88 | printk(BIOS_NOTICE, "done!\n"); |
| 89 | } |
| 90 | |
| 91 | static void finalize_boot(void *unused) |
| 92 | { |
| 93 | /* Set coreboot ready LED. */ |
| 94 | gpio_output(CNV_RGI_DT, 1); |
| 95 | } |
| 96 | |
| 97 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); |
| 98 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |