Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT |
| 3 | |
| 4 | device cpu_cluster 0 on |
| 5 | device lapic 0 on end |
| 6 | end |
| 7 | |
| 8 | device domain 0 on |
| 9 | device pci 00.0 on end # Host Bridge |
| 10 | device pci 01.0 on # PEG x8 / Slot 2 |
| 11 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X" |
| 12 | end |
| 13 | device pci 01.1 on # PEG x4 or x8 / Slot 6 |
| 14 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X" |
| 15 | end |
| 16 | device pci 01.2 on # PEG x4 or disabled / Slot 4 |
| 17 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X" |
| 18 | end |
| 19 | device pci 04.0 on end # SA Thermal device |
| 20 | device pci 04.0 on end # Intel Xeon E3 |
| 21 | device pci 08.0 on end # Gaussian Mixture |
| 22 | device pci 12.0 on end # Thermal Subsystem |
| 23 | device pci 14.0 on end # USB xHCI |
Patrick Rudolph | ae758fa | 2020-06-18 11:34:19 +0200 | [diff] [blame] | 24 | device pci 14.1 off end # USB xDCI (OTG) |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 25 | device pci 14.2 on end # RAM controller |
| 26 | device pci 14.5 off end # SDCard |
| 27 | |
| 28 | device pci 16.0 on end # Management Engine Interface |
| 29 | device pci 16.1 on end # Management Engine Interface |
| 30 | device pci 16.4 on end # Management Engine Interface |
| 31 | device pci 17.0 on end # SATA |
| 32 | device pci 1d.6 on |
| 33 | device pci 00.0 on # Aspeed PCI Bridge |
| 34 | device pci 00.0 on end # Aspeed 2500 VGA |
| 35 | end |
| 36 | end # PCIe |
Elyes HAOUAS | bda27cd | 2020-06-27 07:17:16 +0200 | [diff] [blame^] | 37 | device pci 1f.0 on # LPC Interface |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 38 | chip drivers/pc80/tpm |
| 39 | device pnp 0c31.0 on end |
| 40 | end |
| 41 | # AST2500, but not enabled to decode LPC cycles |
| 42 | end |
| 43 | device pci 1f.3 on end |
| 44 | device pci 1f.4 on end # SMBus |
| 45 | device pci 1f.5 on end # PCH SPI |
| 46 | end |
| 47 | |
| 48 | end |