Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 2 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 3 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 5 | #include <device/device.h> |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 7 | #include <device/smbus_host.h> |
Elyes HAOUAS | 27ce8e3 | 2020-08-12 09:50:48 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/common/pmbase.h> |
Elyes Haouas | bd5fe98 | 2024-04-09 17:34:33 +0200 | [diff] [blame^] | 9 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 10 | #include "pch.h" |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 11 | #include "chip.h" |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 12 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 13 | #if CONFIG(INTEL_LYNXPOINT_LP) |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 14 | #include "lp_gpio.h" |
| 15 | #else |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 16 | #include <southbridge/intel/common/gpio.h> |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 17 | #endif |
| 18 | |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 19 | enum pch_platform_type get_pch_platform_type(void) |
| 20 | { |
| 21 | const u16 did = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); |
| 22 | |
| 23 | /* Check if this is a LPT-LP or WPT-LP device ID */ |
| 24 | if ((did & 0xff00) == 0x9c00) |
| 25 | return PCH_TYPE_ULT; |
| 26 | |
| 27 | /* Non-LP laptop SKUs have an odd device ID (least significant bit is one) */ |
| 28 | if (did & 1) |
| 29 | return PCH_TYPE_MOBILE; |
| 30 | |
| 31 | /* Desktop and Server SKUs have an even device ID */ |
| 32 | return PCH_TYPE_DESKTOP; |
| 33 | } |
| 34 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 35 | static void pch_enable_bars(void) |
| 36 | { |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 37 | pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 38 | |
| 39 | pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); |
| 40 | /* Enable ACPI BAR */ |
Angel Pons | f471171 | 2020-11-04 00:38:28 +0100 | [diff] [blame] | 41 | pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 42 | |
Angel Pons | 84fa224 | 2020-10-24 11:53:47 +0200 | [diff] [blame] | 43 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 44 | |
| 45 | /* Enable GPIO functionality. */ |
| 46 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 47 | } |
| 48 | |
| 49 | static void pch_generic_setup(void) |
| 50 | { |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 51 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 52 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Elyes HAOUAS | 27ce8e3 | 2020-08-12 09:50:48 +0200 | [diff] [blame] | 53 | write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 54 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 55 | } |
| 56 | |
Stefan Reinauer | 779e178 | 2013-10-07 16:29:54 -0700 | [diff] [blame] | 57 | void pch_enable_lpc(void) |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 58 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 59 | const struct device *dev = pcidev_on_root(0x1f, 0); |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 60 | const struct southbridge_intel_lynxpoint_config *config = NULL; |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 61 | |
| 62 | /* Set COM1/COM2 decode range */ |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 63 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 64 | |
Duncan Laurie | 7a3fd4d | 2013-03-07 14:00:43 -0800 | [diff] [blame] | 65 | /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ |
Duncan Laurie | a103d07 | 2013-05-01 11:12:53 -0700 | [diff] [blame] | 66 | u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | |
Duncan Laurie | 7a3fd4d | 2013-03-07 14:00:43 -0800 | [diff] [blame] | 67 | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 68 | pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); |
| 69 | |
| 70 | /* Set up generic decode ranges */ |
| 71 | if (!dev) |
| 72 | return; |
| 73 | if (dev->chip_info) |
| 74 | config = dev->chip_info; |
| 75 | if (!config) |
| 76 | return; |
| 77 | |
| 78 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 79 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 80 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 81 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 82 | } |
| 83 | |
Tristan Corrick | 655ef61 | 2018-10-31 02:26:19 +1300 | [diff] [blame] | 84 | void __weak mainboard_config_superio(void) |
| 85 | { |
| 86 | } |
| 87 | |
Angel Pons | 30931f5 | 2021-03-12 13:06:45 +0100 | [diff] [blame] | 88 | void early_pch_init(void) |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 89 | { |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 90 | pch_enable_bars(); |
| 91 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 92 | #if CONFIG(INTEL_LYNXPOINT_LP) |
Angel Pons | 88f94a9 | 2021-03-19 15:13:46 +0100 | [diff] [blame] | 93 | setup_pch_lp_gpios(mainboard_lp_gpio_map); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 94 | #else |
Angel Pons | 03f0e43 | 2020-07-03 13:51:15 +0200 | [diff] [blame] | 95 | setup_pch_gpios(&mainboard_gpio_map); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 96 | #endif |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 97 | pch_generic_setup(); |
| 98 | |
| 99 | /* Enable SMBus for reading SPDs. */ |
| 100 | enable_smbus(); |
| 101 | |
Angel Pons | 55d148c | 2020-07-03 12:41:48 +0200 | [diff] [blame] | 102 | /* Enable IOAPIC */ |
| 103 | RCBA16(OIC) = 0x0100; |
| 104 | |
| 105 | /* PCH BWG says to read back the IOAPIC enable register */ |
Angel Pons | 8cb8374 | 2020-10-17 18:28:29 +0200 | [diff] [blame] | 106 | (void)RCBA16(OIC); |
Duncan Laurie | 18af4d2 | 2012-12-19 13:17:06 -0800 | [diff] [blame] | 107 | |
| 108 | /* Mainboard RCBA settings */ |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 109 | mainboard_config_rcba(); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 110 | |
Angel Pons | b4f9833 | 2020-07-03 12:49:05 +0200 | [diff] [blame] | 111 | RCBA32_OR(FD, PCH_DISABLE_ALWAYS); |
| 112 | |
Angel Pons | 2cdf8bd | 2020-11-04 17:47:45 +0100 | [diff] [blame] | 113 | RCBA32(0x2088) = 0x00109000; |
| 114 | |
| 115 | RCBA32_OR(0x20ac, 1 << 30); |
| 116 | |
| 117 | if (!pch_is_lp()) { |
| 118 | RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); |
| 119 | RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); |
| 120 | |
| 121 | RCBA32(0x2324) = 0x00854c74; |
| 122 | } |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 123 | } |