blob: 08a4cf8e13071e40ed7cb099b696075de63bc291 [file] [log] [blame]
Gabe Blackd40be112013-10-09 23:45:07 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright 2013 Google Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <console/console.h>
23#include <device/device.h>
Jimmy Zhangbd5925a2014-03-10 12:42:05 -070024#include <arch/io.h>
Gabe Blackd40be112013-10-09 23:45:07 -070025#include <soc/nvidia/tegra/dc.h>
Tom Warren64982c502014-01-23 13:37:50 -070026#include <soc/nvidia/tegra124/sdram.h>
Jimmy Zhangbd5925a2014-03-10 12:42:05 -070027#include "chip.h"
Tom Warren64982c502014-01-23 13:37:50 -070028#include <soc/display.h>
Gabe Blackd40be112013-10-09 23:45:07 -070029
30/* this sucks, but for now, fb size/location are hardcoded.
31 * Will break if we get 2. Sigh.
32 * We assume it's all multiples of MiB for MMUs sake.
33 */
34static void soc_enable(device_t dev)
35{
Tom Warren64982c502014-01-23 13:37:50 -070036 u32 lcdbase = fb_base_mb();
Gabe Blackd40be112013-10-09 23:45:07 -070037 unsigned long fb_size = FB_SIZE_MB;
Tom Warren64982c502014-01-23 13:37:50 -070038
Gabe Blackd40be112013-10-09 23:45:07 -070039 ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
Gabe Black5cbbc702014-02-08 05:17:38 -080040 (sdram_max_addressable_mb() - fb_size)*KiB -
41 CONFIG_SYS_SDRAM_BASE/KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070042 mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
Gabe Black5cbbc702014-02-08 05:17:38 -080043
44 u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB;
45
46 if (sdram_end_mb > sdram_max_addressable_mb())
47 ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
48 (sdram_end_mb - sdram_max_addressable_mb())*KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070049}
50
51static void soc_init(device_t dev)
52{
53 display_startup(dev);
54 printk(BIOS_INFO, "CPU: Tegra124\n");
55}
56
Gabe Blackd40be112013-10-09 23:45:07 -070057static struct device_operations soc_ops = {
Edward O'Callaghan0625a8b2014-10-31 08:03:16 +110058 .read_resources = DEVICE_NOOP,
59 .set_resources = DEVICE_NOOP,
Gabe Blackd40be112013-10-09 23:45:07 -070060 .enable_resources = soc_enable,
61 .init = soc_init,
62 .scan_bus = 0,
63};
64
65static void enable_tegra124_dev(device_t dev)
66{
67 dev->ops = &soc_ops;
68}
69
70struct chip_operations soc_nvidia_tegra124_ops = {
71 CHIP_NAME("SOC Nvidia Tegra124")
72 .enable_dev = enable_tegra124_dev,
73};