Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright 2013 Google Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame^] | 24 | #include <arch/io.h> |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 25 | #include <soc/nvidia/tegra/dc.h> |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 26 | #include <soc/nvidia/tegra124/sdram.h> |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame^] | 27 | #include "chip.h" |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 28 | #include <soc/display.h> |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 29 | |
| 30 | /* this sucks, but for now, fb size/location are hardcoded. |
| 31 | * Will break if we get 2. Sigh. |
| 32 | * We assume it's all multiples of MiB for MMUs sake. |
| 33 | */ |
| 34 | static void soc_enable(device_t dev) |
| 35 | { |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 36 | u32 lcdbase = fb_base_mb(); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 37 | unsigned long fb_size = FB_SIZE_MB; |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 38 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 39 | ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 40 | (sdram_max_addressable_mb() - fb_size)*KiB - |
| 41 | CONFIG_SYS_SDRAM_BASE/KiB); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 42 | mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 43 | |
| 44 | u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB; |
| 45 | |
| 46 | if (sdram_end_mb > sdram_max_addressable_mb()) |
| 47 | ram_resource(dev, 2, sdram_max_addressable_mb()*KiB, |
| 48 | (sdram_end_mb - sdram_max_addressable_mb())*KiB); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | static void soc_init(device_t dev) |
| 52 | { |
| 53 | display_startup(dev); |
| 54 | printk(BIOS_INFO, "CPU: Tegra124\n"); |
| 55 | } |
| 56 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 57 | static struct device_operations soc_ops = { |
Edward O'Callaghan | 0625a8b | 2014-10-31 08:03:16 +1100 | [diff] [blame] | 58 | .read_resources = DEVICE_NOOP, |
| 59 | .set_resources = DEVICE_NOOP, |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 60 | .enable_resources = soc_enable, |
| 61 | .init = soc_init, |
| 62 | .scan_bus = 0, |
| 63 | }; |
| 64 | |
| 65 | static void enable_tegra124_dev(device_t dev) |
| 66 | { |
| 67 | dev->ops = &soc_ops; |
| 68 | } |
| 69 | |
| 70 | struct chip_operations soc_nvidia_tegra124_ops = { |
| 71 | CHIP_NAME("SOC Nvidia Tegra124") |
| 72 | .enable_dev = enable_tegra124_dev, |
| 73 | }; |