Xi Chen | 022b1b9 | 2021-02-05 11:45:12 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <emi_hw.h> |
| 5 | #include <emi.h> |
| 6 | #include "dramc_reg_base_addr.h" |
| 7 | #include <dramc_top.h> |
| 8 | #include <soc/emi.h> |
| 9 | |
| 10 | #ifdef LAST_EMI |
| 11 | static LAST_EMI_INFO_T* last_emi_info_ptr; |
| 12 | #endif |
| 13 | |
| 14 | static inline unsigned int mt_emi_sync_read(unsigned long long addr) |
| 15 | { |
| 16 | dsb(); |
| 17 | return *((volatile unsigned int *)addr); |
| 18 | } |
| 19 | |
| 20 | #define mt_emi_sync_write(addr, value) \ |
| 21 | do { \ |
| 22 | *((volatile unsigned int *)(addr)) = value; \ |
| 23 | dsb(); \ |
| 24 | } while (0) |
| 25 | |
| 26 | #define mt_emi_sync_write_or(addr, or_value) \ |
| 27 | do { \ |
| 28 | mt_emi_sync_write(addr, \ |
| 29 | mt_emi_sync_read(addr) | or_value); \ |
| 30 | } while (0) |
| 31 | |
| 32 | static void emi_cen_config(void) |
| 33 | { |
| 34 | #ifndef ONE_CH |
| 35 | #ifdef RANK_512MB // => 2channel , dual rank , total=2G |
| 36 | mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154); |
| 37 | #else //RANK_1G => 2channel , dual rank , total=4G |
| 38 | mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154); |
| 39 | #endif |
| 40 | #else |
| 41 | #ifdef RANK_512MB |
| 42 | mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a054); |
| 43 | #else |
| 44 | mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f054); |
| 45 | #endif |
| 46 | #endif |
| 47 | |
| 48 | // overhead: 20190821 item1 - synced |
| 49 | mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4 - r1 overhead // TBD - change to 4266 |
| 50 | mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8 - r5 overhead // TBD - change to 4266 |
| 51 | mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9 overhead // TBD - change to 4266 |
| 52 | mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead // TBD - change to 4266 |
| 53 | mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4 - r1 overhead |
| 54 | mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8 - r5 overhead |
| 55 | mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9 overhead |
| 56 | mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead |
| 57 | mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4 - r1 overhead |
| 58 | mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8 - r5 overhead |
| 59 | mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9 overhead |
| 60 | mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead |
| 61 | mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4 - r1 overhead |
| 62 | mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8 - r5 overhead |
| 63 | mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9 overhead |
| 64 | mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead |
| 65 | mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4 - r1 overhead |
| 66 | mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8 - r5 overhead |
| 67 | mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9 overhead |
| 68 | mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead |
| 69 | mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4 - r1 overhead |
| 70 | mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8 - r5 overhead |
| 71 | mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9 overhead |
| 72 | mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead |
| 73 | mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800 (1:4) r12 - r9 overhead |
| 74 | mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800 (1:4) r4 - r1 overhead |
| 75 | mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800 (1:4) r16 - r13 overhead |
| 76 | mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800 (1:4) r8 - r5 overhead |
| 77 | mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800 (1:4) r12 - r9 overhead |
| 78 | mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800 (1:4) r4 - r1 overhead |
| 79 | mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800 (1:4) r16 - r13 overhead |
| 80 | mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800 (1:4) r8 - r5 overhead |
| 81 | |
| 82 | mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead // TBD - change to 4266 |
| 83 | mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead // TBD - change to 4266 |
| 84 | mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead |
| 85 | mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead |
| 86 | mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8 - r2 non-align overhead |
| 87 | mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead |
| 88 | mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8 - r2 non-align overhead |
| 89 | mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead |
| 90 | mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8 - r2 non-align overhead |
| 91 | mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead |
| 92 | mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8 - r2 non-align overhead |
| 93 | mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead |
| 94 | mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800 (1:4) r8 - r2 non-align overhead |
| 95 | mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800 (1:4) r16 - r10 non-align overhead |
| 96 | mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800 (1:4) r8 - r2 non-align overhead |
| 97 | mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800 (1:4) r16 - r10 non-align overhead |
| 98 | |
| 99 | // |
| 100 | mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a); |
| 101 | mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042); |
| 102 | mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000); |
| 103 | mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x00000083); |
| 104 | mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210); |
| 105 | mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802); |
| 106 | mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000); |
| 107 | mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal rea d/write :8/7 |
| 108 | mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000); |
| 109 | mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1 |
| 110 | mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1 |
| 111 | mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123); |
| 112 | mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123); |
| 113 | mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8); |
| 114 | mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525); |
| 115 | mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8); |
| 116 | mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525); |
| 117 | mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter di v2, [4]=1 |
| 118 | mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014); |
| 119 | mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000); |
| 120 | mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244); |
| 121 | mt_emi_sync_write(EMI_APB_BASE+0x00000108,0x10107044); |
| 122 | mt_emi_sync_write(EMI_APB_BASE+0x00000110,0x343450df); |
| 123 | mt_emi_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0); |
| 124 | mt_emi_sync_write(EMI_APB_BASE+0x00000120,0x10106048); |
| 125 | mt_emi_sync_write(EMI_APB_BASE+0x00000128,0x343450df); |
| 126 | mt_emi_sync_write(EMI_APB_BASE+0x00000130,0x83837044); |
| 127 | mt_emi_sync_write(EMI_APB_BASE+0x00000138,0x83837044); |
| 128 | mt_emi_sync_write(EMI_APB_BASE+0x00000140,0x00007108); |
| 129 | mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108); |
| 130 | mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a4000); |
| 131 | mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00); |
| 132 | mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor |
| 133 | mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008); |
| 134 | mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff); |
| 135 | mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101); |
| 136 | mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424); |
| 137 | mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101); |
| 138 | mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050); |
| 139 | mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT, |
| 140 | mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003); |
| 141 | mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff); |
| 142 | mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update |
| 143 | mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8); |
| 144 | mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b); |
| 145 | mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290); |
| 146 | mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200); |
| 147 | mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000); |
| 148 | mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000); |
| 149 | mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold |
| 150 | mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); |
| 151 | mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5); |
| 152 | mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update |
| 153 | mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d); |
| 154 | mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59); |
| 155 | mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff); |
| 156 | mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff); |
| 157 | mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff); |
| 158 | mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b); |
| 159 | mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update |
| 160 | mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185); |
| 161 | mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update |
| 162 | mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185); |
| 163 | mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update |
| 164 | mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff); |
| 165 | mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff); |
| 166 | mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff); |
| 167 | mt_emi_sync_write(EMI_APB_BASE+0x00000920,0xffffffff); |
| 168 | mt_emi_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff); |
| 169 | mt_emi_sync_write(EMI_APB_BASE+0x00000930,0xffffffff); |
| 170 | mt_emi_sync_write(EMI_APB_BASE+0x00000934,0xffffffff); |
| 171 | mt_emi_sync_write(EMI_APB_BASE+0x00000938,0xffffffff); |
| 172 | mt_emi_sync_write(EMI_APB_BASE+0x000009f0,0x41547082); |
| 173 | mt_emi_sync_write(EMI_APB_BASE+0x000009f4,0x38382a38); |
| 174 | mt_emi_sync_write(EMI_APB_BASE+0x000009f8,0x000001d4); |
| 175 | mt_emi_sync_write(EMI_APB_BASE+0x000009fc,0x00000190); |
| 176 | mt_emi_sync_write(EMI_APB_BASE+0x00000b00,0x0000012c); |
| 177 | mt_emi_sync_write(EMI_APB_BASE+0x00000b04,0x000000ed); |
| 178 | mt_emi_sync_write(EMI_APB_BASE+0x00000b08,0x000000c8); |
| 179 | mt_emi_sync_write(EMI_APB_BASE+0x00000b0c,0x00000096); |
| 180 | mt_emi_sync_write(EMI_APB_BASE+0x00000b10,0x000000c8); |
| 181 | mt_emi_sync_write(EMI_APB_BASE+0x00000b14,0x000000c8); |
| 182 | mt_emi_sync_write(EMI_APB_BASE+0x00000b28,0x26304048); |
| 183 | mt_emi_sync_write(EMI_APB_BASE+0x00000b2c,0x20201820); |
| 184 | mt_emi_sync_write(EMI_APB_BASE+0x00000b60,0x181e282f); |
| 185 | mt_emi_sync_write(EMI_APB_BASE+0x00000b64,0x14140f18); |
| 186 | mt_emi_sync_write(EMI_APB_BASE+0x00000b98,0x7496c8ea); |
| 187 | mt_emi_sync_write(EMI_APB_BASE+0x00000b9c,0x64644b64); |
| 188 | mt_emi_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101); |
| 189 | mt_emi_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101); |
| 190 | mt_emi_sync_write(EMI_APB_BASE+0x00000c08,0x7496c8ea); // 20190821 item3 - synced // TB D- 4266 may need changes |
| 191 | mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64); // 20190821 item3 - synced // TB D- 4266 may need changes |
| 192 | mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101); |
| 193 | mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101); |
| 194 | mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); //ignore wff threshold |
| 195 | mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8); |
| 196 | mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b); |
| 197 | mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290); |
| 198 | mt_emi_sync_write(EMI_APB_BASE+0x00000c8c,0x00000200); |
| 199 | mt_emi_sync_write(EMI_APB_BASE+0x00000c90,0x000001b5); |
| 200 | mt_emi_sync_write(EMI_APB_BASE+0x00000c94,0x0000014b); |
| 201 | mt_emi_sync_write(EMI_APB_BASE+0x00000c98,0x00000185); |
| 202 | mt_emi_sync_write(EMI_APB_BASE+0x00000c9c,0x00000185); |
| 203 | mt_emi_sync_write(EMI_APB_BASE+0x00000cb0,0x52698ca0); |
| 204 | mt_emi_sync_write(EMI_APB_BASE+0x00000cb4,0x46463546); |
| 205 | mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101); |
| 206 | mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101); |
| 207 | |
| 208 | mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet |
| 209 | mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet |
| 210 | mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0 |
| 211 | mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1 |
| 212 | mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet |
| 213 | mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet |
| 214 | mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0 |
| 215 | mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1 |
| 216 | mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet |
| 217 | mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet |
| 218 | mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1 |
| 219 | mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet |
| 220 | mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet |
| 221 | mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet |
| 222 | mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet |
| 223 | mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet |
| 224 | mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet |
| 225 | mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet |
| 226 | mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0 |
| 227 | mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1 |
| 228 | mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet |
| 229 | mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet |
| 230 | mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet |
| 231 | mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet |
| 232 | mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet |
| 233 | mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0 |
| 234 | mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1 |
| 235 | mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select |
| 236 | mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select |
| 237 | mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh |
| 238 | mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select |
| 239 | mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select |
| 240 | mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select |
| 241 | mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select |
| 242 | mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR |
| 243 | mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select |
| 244 | mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select |
| 245 | mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select |
| 246 | mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select |
| 247 | mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB |
| 248 | mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control |
| 249 | mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166); |
| 250 | mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff); |
| 251 | mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff); |
| 252 | mt_emi_sync_write(EMI_APB_BASE+0x00000e14,0x00400166); |
| 253 | mt_emi_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff); |
| 254 | mt_emi_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff); |
| 255 | mt_emi_sync_write(EMI_APB_BASE+0x00000e24,0x00000266); |
| 256 | mt_emi_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff); |
| 257 | mt_emi_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff); |
| 258 | mt_emi_sync_write(EMI_APB_BASE+0x00000e34,0x00400266); |
| 259 | mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff); |
| 260 | mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff); |
| 261 | |
| 262 | // Added by Wei-Lun - START |
| 263 | // prtcl chker - golden setting |
| 264 | mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc |
| 265 | mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl |
| 266 | mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk |
| 267 | |
| 268 | mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff); |
| 269 | mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85); |
| 270 | mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk |
| 271 | |
| 272 | mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff); |
| 273 | mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85); |
| 274 | mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk |
| 275 | |
| 276 | mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff); |
| 277 | mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85); |
| 278 | mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk |
| 279 | |
| 280 | mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff); |
| 281 | mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85); |
| 282 | mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk |
| 283 | |
| 284 | mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff); |
| 285 | mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85); |
| 286 | mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk |
| 287 | |
| 288 | mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff); |
| 289 | mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85); |
| 290 | mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk |
| 291 | |
| 292 | mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff); |
| 293 | mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85); |
| 294 | mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk |
| 295 | |
| 296 | // maxbw monitor - golden setting |
| 297 | |
| 298 | // enable dbw0 cnter for max bw correlation (m3/4 no filters are enabled) |
| 299 | // Added by Wei-Lun - END |
| 300 | |
| 301 | //weilun for new feature |
| 302 | mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_em i rw switching shf |
| 303 | |
| 304 | // cen_emi timeout value |
| 305 | mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060); |
| 306 | mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060); |
| 307 | |
| 308 | // fine-grained qos |
| 309 | mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000); |
| 310 | |
| 311 | // ostd->bw |
| 312 | mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff); |
| 313 | mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c); |
| 314 | mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff); |
| 315 | mt_emi_sync_write(EMI_APB_BASE+0x0000077c,0x00ffffff); |
| 316 | mt_emi_sync_write(EMI_APB_BASE+0x00000784,0xffff00ff); |
| 317 | mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff); |
| 318 | mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000); |
| 319 | |
| 320 | // hash rule |
| 321 | mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000); |
| 322 | } |
| 323 | |
| 324 | static void emi_chn_config(void) |
| 325 | { |
| 326 | #ifdef RANK_512MB // => 2channel , dual rank , total=2G |
| 327 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400a051); |
| 328 | #else //RANK_1G => 2channel , dual rank , total=4G |
| 329 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400f051); |
| 330 | #endif |
| 331 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000008,0x00ff6048); |
| 332 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000010,0x00000004); |
| 333 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000018,0x99f08c03); |
| 334 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000) |
| 335 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]= 2 |
| 336 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN |
| 337 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000058,0x00000000); |
| 338 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000090,0x000002ff); |
| 339 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000098,0x00003111); //mw2 |
| 340 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000140,0x22607188); |
| 341 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000144,0x22607188); |
| 342 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000148,0x3719595e); // chuan |
| 343 | mt_emi_sync_write(CHN0_EMI_BASE+0x0000014c,0x2719595e); // chuan |
| 344 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000150,0x64f3ff79); |
| 345 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000154,0x64f3ff79); // update timeout settin g: bit 12~15 |
| 346 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000158,0x011b0868); |
| 347 | |
| 348 | // #ifdef SCN_ICFP |
| 349 | // mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x88410222); // Stop urgent read f irst when write command buffer remain < 8 |
| 350 | // #else //SCN_UI |
| 351 | // mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x82410222); // Stop urgent read f irst when write command buffer remain < 2 |
| 352 | // #endif |
| 353 | |
| 354 | mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0xa7414222); // Stop urgent read firs t when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27: 24] wr_rsv_thr_h, |
| 355 | mt_emi_sync_write(CHN0_EMI_BASE+0x0000016c,0x0000f801); |
| 356 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000170,0x40000000); |
| 357 | mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration |
| 358 | mt_emi_sync_write(CHN0_EMI_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration |
| 359 | mt_emi_sync_write(CHN0_EMI_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration |
| 360 | mt_emi_sync_write(CHN0_EMI_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0 |
| 361 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000080,0xaa0148ff); |
| 362 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000088,0xaa6168ff); |
| 363 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000404,0xaa516cff); |
| 364 | mt_emi_sync_write(CHN0_EMI_BASE+0x00000408,0xaa0140ff); |
| 365 | mt_emi_sync_write(CHN0_EMI_BASE+0x0000040c,0x9f658633); |
| 366 | } |
| 367 | |
| 368 | static void emi_sw_setting(void) |
| 369 | { |
| 370 | int emi_dcm; |
| 371 | /* Enable MPU violation interrupt to MD for D1 and D7 */ |
| 372 | *((volatile unsigned int *)EMI_MPU_CTRL_D(1)) |= 0x10; |
| 373 | *((volatile unsigned int *)EMI_MPU_CTRL_D(7)) |= 0x10; |
| 374 | |
| 375 | /* for DVFS BW monitor */ |
| 376 | *((volatile unsigned int *) EMI_BWCT0) = 0x05008305; |
| 377 | *((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF8705; |
| 378 | *((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF8A05; |
| 379 | *((volatile unsigned int *) EMI_THRO_CTRL1) |= 0x300; |
| 380 | |
| 381 | #ifdef LAST_EMI |
| 382 | last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI); |
| 383 | if (last_emi_info_ptr->isu_magic != LAST_EMI_MAGIC_PATTERN) { |
| 384 | last_emi_info_ptr->isu_magic = LAST_EMI_MAGIC_PATTERN; |
| 385 | last_emi_info_ptr->isu_version = 0xFFFFFFFF; |
| 386 | last_emi_info_ptr->isu_dram_type = 0; |
| 387 | last_emi_info_ptr->isu_diff_us = 0; |
| 388 | last_emi_info_ptr->os_flag_sspm = 0; |
| 389 | last_emi_info_ptr->os_flag_ap = 0; |
| 390 | } |
| 391 | emi_isu = atoi(dconfig_getenv("emi_isu")); |
| 392 | emi_log("[EMI DOE] emi_isu %d\n", emi_isu); |
| 393 | if (emi_isu == 1) |
| 394 | last_emi_info_ptr->isu_ctrl = 0xDECDDECD; |
| 395 | else if (emi_isu == 2) |
| 396 | last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0; |
| 397 | else { |
| 398 | #if CFG_LAST_EMI_BW_DUMP |
| 399 | last_emi_info_ptr->isu_ctrl = 0xDECDDECD; |
| 400 | #else |
| 401 | last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0; |
| 402 | #endif |
| 403 | } |
| 404 | #endif |
| 405 | *((volatile unsigned int *)0x10219858) |= 0x1 << 11; |
| 406 | emi_dcm = 0;//atoi(dconfig_getenv("emi_dcm")); |
| 407 | emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm); |
| 408 | if (emi_dcm == 1) { |
| 409 | *((volatile unsigned int *)EMI_CONM) &= ~0xFF000000; |
| 410 | *((volatile unsigned int *)EMI_CONN) &= ~0xFF000000; |
| 411 | } else if (emi_dcm == 2) { |
| 412 | *((volatile unsigned int *)EMI_CONM) |= 0xFF000000; |
| 413 | *((volatile unsigned int *)EMI_CONN) |= 0xFF000000; |
| 414 | } |
| 415 | dsb(); |
| 416 | } |
| 417 | |
| 418 | void emi_init(void) |
| 419 | { |
| 420 | /* emi_config_lpddr4_2ch_golden_20191202_1000.c */ |
| 421 | //Broadcast on |
| 422 | mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x0000007f); |
| 423 | |
| 424 | emi_cen_config(); |
| 425 | emi_chn_config(); |
| 426 | |
| 427 | //Broadcast off |
| 428 | mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x00000000); |
| 429 | } |
| 430 | |
| 431 | void emi_init2(void) |
| 432 | { |
| 433 | unsigned int emi_temp_data; |
| 434 | |
| 435 | //Broadcast on |
| 436 | mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x0000007f); |
| 437 | |
| 438 | mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); // [0] EMI enable |
| 439 | mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); //[10] EMI enable |
| 440 | |
| 441 | #ifdef MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING |
| 442 | |
| 443 | mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg in terrupt |
| 444 | |
| 445 | // Clear rank_arb_en |
| 446 | emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x000001b0); // read ch0 |
| 447 | emi_temp_data = emi_temp_data & ~(0x1); |
| 448 | mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to all channel |
| 449 | // auto-config rank_arb_en according to dual_rank_en setting |
| 450 | // assume all channel with same configuration |
| 451 | emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x00000000); // read ch0 |
| 452 | emi_temp_data = emi_temp_data & 0x1; |
| 453 | mt_emi_sync_write_or(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to a ll channel |
| 454 | |
| 455 | // ----- from dcm_setting.c ----- |
| 456 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF); |
| 457 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF); |
| 458 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF); |
| 459 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x10C, 0xFFFFFFFF); |
| 460 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x110, 0x01F00000); |
| 461 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x114, 0xC0040180); |
| 462 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x118, 0x00000000); |
| 463 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x11C, 0x00000003); |
| 464 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x120, 0x0C000000); |
| 465 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x124, 0x00C00000); |
| 466 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x128, 0x01F08000); |
| 467 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x12C, 0x00000000); |
| 468 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x130, 0x20003040); |
| 469 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x134, 0x00000000); |
| 470 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x138, 0x00001000); |
| 471 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x13C, 0x00000000); |
| 472 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x140, 0x10020F20); |
| 473 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x144, 0x00019000); |
| 474 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x148, 0x040A0818); |
| 475 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x14C, 0x00000370); |
| 476 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x150, 0xC001C080); |
| 477 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x154, 0x33000E01); |
| 478 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x158, 0x180067E1); |
| 479 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x15C, 0x000C008C); |
| 480 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x160, 0x020C0008); |
| 481 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x164, 0x0C00007E); |
| 482 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x168, 0x80050006); |
| 483 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x16C, 0x00030000); |
| 484 | |
| 485 | |
| 486 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x0000000F); |
| 487 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0x00000000); |
| 488 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x030, 0x001F0044); |
| 489 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0x200000FF); |
| 490 | |
| 491 | mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg |
| 492 | |
| 493 | #ifdef MARGAUX_EMI_MP_SETTING |
| 494 | // Enable rdata_prty_gen & wdata_prty_chk |
| 495 | |
| 496 | // emi bus parity workaround |
| 497 | emi_temp_data = mt_emi_sync_read(0x40000000); |
| 498 | mt_emi_sync_write(0x40000000, emi_temp_data); |
| 499 | emi_temp_data = mt_emi_sync_read(0x40000100); |
| 500 | mt_emi_sync_write(0x40000100, emi_temp_data); |
| 501 | emi_temp_data = mt_emi_sync_read(0x40000200); |
| 502 | mt_emi_sync_write(0x40000200, emi_temp_data); |
| 503 | emi_temp_data = mt_emi_sync_read(0x40000300); |
| 504 | mt_emi_sync_write(0x40000300, emi_temp_data); |
| 505 | |
| 506 | mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); // enable cen_emi parity (w) |
| 507 | mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000004); // enable chn_emi par ity |
| 508 | |
| 509 | /*TINFO="Enable APMCU Early CKE"*/ |
| 510 | //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000); |
| 511 | //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4); |
| 512 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007); // set disph_chn_en = 0x7 |
| 513 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1 |
| 514 | |
| 515 | /*TINFO="read emi_reg_pd then write apmcu config reg"*/ |
| 516 | emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050); |
| 517 | emi_temp_data = emi_temp_data & 0xf; |
| 518 | mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data); |
| 519 | |
| 520 | /*TINFO="Enable EMI wdata bus encode function"*/ |
| 521 | mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus e ncode // *EMI_CONN |= (0x1 << 21); |
| 522 | mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000010); // enable chn_emi wda ta bus encode // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4); |
| 523 | #else |
| 524 | // MP_dsim_v02 test (from v01) - all fr |
| 525 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000); |
| 526 | mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0xA0000000); |
| 527 | #endif |
| 528 | |
| 529 | #endif |
| 530 | |
| 531 | mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG |
| 532 | |
| 533 | //Broadcast off |
| 534 | mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000); |
| 535 | |
| 536 | emi_sw_setting(); |
| 537 | } |
| 538 | |
| 539 | int get_row_width_by_emi(unsigned int rank) |
| 540 | { |
| 541 | unsigned int emi_cona; |
| 542 | unsigned int shift_row, shift_ext; |
| 543 | int row_width; |
| 544 | |
| 545 | if (rank == 0) { |
| 546 | shift_row = 12; |
| 547 | shift_ext = 22; |
| 548 | } else if (rank == 1) { |
| 549 | shift_row = 14; |
| 550 | shift_ext = 23; |
| 551 | } else |
| 552 | return -1; |
| 553 | |
| 554 | emi_cona = mt_emi_sync_read(EMI_CONA); |
| 555 | row_width = |
| 556 | ((emi_cona >> shift_row) & 0x3) | |
| 557 | ((emi_cona >> shift_ext) & 0x4); |
| 558 | |
| 559 | return (row_width + 13); |
| 560 | } |
| 561 | |
| 562 | int get_channel_nr_by_emi(void) |
| 563 | { |
| 564 | int channel_nr; |
| 565 | |
| 566 | channel_nr = 0x1 << ((mt_emi_sync_read(EMI_CONA) >> 8) & 0x3); |
| 567 | |
| 568 | return channel_nr; |
| 569 | } |
| 570 | |
| 571 | int get_rank_nr_by_emi(void) |
| 572 | { |
| 573 | unsigned int cen_emi_cona = mt_emi_sync_read(EMI_CONA); |
| 574 | |
| 575 | if (cen_emi_cona & (0x3 << 16)) |
| 576 | return 2; |
| 577 | else |
| 578 | return 1; |
| 579 | } |
| 580 | |
| 581 | _Static_assert(DRAMC_MAX_RK > 1, "rank number is violated"); |
| 582 | void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]) |
| 583 | { |
| 584 | unsigned int quad_ch_ratio; |
| 585 | unsigned long long ch0_rank0_size, ch0_rank1_size; |
| 586 | unsigned long long ch1_rank0_size, ch1_rank1_size; |
| 587 | unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH); |
Xi Chen | 022b1b9 | 2021-02-05 11:45:12 +0800 | [diff] [blame] | 588 | |
| 589 | dram_rank_size[0] = 0; |
| 590 | dram_rank_size[1] = 0; |
| 591 | |
| 592 | ch0_rank0_size = (cen_emi_conh >> 16) & 0xF; |
| 593 | ch0_rank1_size = (cen_emi_conh >> 20) & 0xF; |
| 594 | ch1_rank0_size = (cen_emi_conh >> 24) & 0xF; |
| 595 | ch1_rank1_size = (cen_emi_conh >> 28) & 0xF; |
| 596 | |
| 597 | quad_ch_ratio = (get_rank_nr_by_emi() == 4)? 2 : 1; |
| 598 | ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28; |
| 599 | ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28; |
| 600 | ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28; |
| 601 | ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28; |
| 602 | |
| 603 | if(ch0_rank0_size == 0) { |
| 604 | die("[EMI] undefined CONH for CH0 RANK0\n"); |
| 605 | } |
| 606 | dram_rank_size[0] += ch0_rank0_size; |
| 607 | |
| 608 | if (get_rank_nr_by_emi() > 1) { |
| 609 | if(ch0_rank1_size == 0) { |
| 610 | die("[EMI] undefined CONH for CH0 RANK1\n"); |
| 611 | } |
| 612 | dram_rank_size[1] += ch0_rank1_size; |
| 613 | } |
| 614 | |
| 615 | if(get_channel_nr_by_emi() > 1) { |
| 616 | if(ch1_rank0_size == 0) { |
| 617 | die("[EMI] undefined CONH for CH1 RANK0\n"); |
| 618 | } |
| 619 | dram_rank_size[0] += ch1_rank0_size; |
| 620 | |
| 621 | if (get_rank_nr_by_emi() > 1) { |
| 622 | if(ch1_rank1_size == 0) { |
| 623 | die("[EMI] undefined CONH for CH1 RANK1\n"); |
| 624 | } |
| 625 | dram_rank_size[1] += ch1_rank1_size; |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | emi_log("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n", |
| 630 | dram_rank_size[0], dram_rank_size[1]); |
| 631 | } |
| 632 | |
| 633 | void set_cen_emi_cona(unsigned int cona_val) |
| 634 | { |
| 635 | mt_emi_sync_write(EMI_CONA, cona_val); |
| 636 | } |
| 637 | |
| 638 | void set_cen_emi_conf(unsigned int conf_val) |
| 639 | { |
| 640 | mt_emi_sync_write(EMI_CONF, conf_val); |
| 641 | } |
| 642 | |
| 643 | void set_cen_emi_conh(unsigned int conh_val) |
| 644 | { |
| 645 | mt_emi_sync_write(EMI_CONH, conh_val); |
| 646 | } |
| 647 | |
| 648 | void set_chn_emi_cona(unsigned int cona_val) |
| 649 | { |
| 650 | mt_emi_sync_write(CHN_EMI_CONA(CHN0_EMI_BASE), cona_val); |
| 651 | mt_emi_sync_write(CHN_EMI_CONA(CHN1_EMI_BASE), cona_val); |
| 652 | } |
| 653 | |
| 654 | void set_chn_emi_conc(unsigned int conc_val) |
| 655 | { |
| 656 | mt_emi_sync_write(CHN_EMI_CONC(CHN0_EMI_BASE), conc_val); |
| 657 | mt_emi_sync_write(CHN_EMI_CONC(CHN1_EMI_BASE), conc_val); |
| 658 | } |
| 659 | |
| 660 | unsigned int get_cen_emi_cona(void) |
| 661 | { |
| 662 | return mt_emi_sync_read(EMI_CONA); |
| 663 | } |
| 664 | |
| 665 | /* assume all chn emi setting are the same */ |
| 666 | unsigned int get_chn_emi_cona(void) |
| 667 | { |
| 668 | unsigned int ch0_emi_cona; |
| 669 | |
| 670 | ch0_emi_cona = mt_emi_sync_read(CHN0_EMI_BASE); |
| 671 | |
| 672 | return ch0_emi_cona; |
| 673 | } |
| 674 | |
| 675 | void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr) |
| 676 | { |
| 677 | unsigned int cen_emi_cona, cen_emi_conf; |
| 678 | unsigned long long rank_size[DRAMC_MAX_RK]; |
| 679 | unsigned int channel_num, rank_num; |
| 680 | unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width; |
| 681 | unsigned int temp; |
| 682 | unsigned int index; |
| 683 | |
| 684 | cen_emi_cona = mt_emi_sync_read(EMI_CONA); |
| 685 | cen_emi_conf = mt_emi_sync_read(EMI_CONF) >> 8; |
| 686 | get_rank_size_by_emi(rank_size); |
| 687 | rank_num = (unsigned int) get_rank_nr_by_emi(); |
| 688 | channel_num = (unsigned int) get_channel_nr_by_emi(); |
| 689 | |
| 690 | phy_addr -= 0x40000000; |
| 691 | for (index = 0; index < rank_num; index++) { |
| 692 | if (phy_addr >= rank_size[index]) |
| 693 | phy_addr -= rank_size[index]; |
| 694 | else |
| 695 | break; |
| 696 | } |
| 697 | |
| 698 | for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) { |
| 699 | bit_xor = (cen_emi_conf >> (4 * (bit_scramble - 11))) & 0xf; |
| 700 | bit_xor &= phy_addr >> 16; |
| 701 | for (bit_shift = 0; bit_shift < 4; bit_shift++) |
| 702 | phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble; |
| 703 | } |
| 704 | |
| 705 | if (channel_num > 1) { |
| 706 | channel_pos = ((cen_emi_cona >> 2) & 0x3) + 7; |
| 707 | |
| 708 | for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) { |
| 709 | if ((unsigned int)(1 << bit_shift) >= channel_num) |
| 710 | break; |
| 711 | channel_width++; |
| 712 | } |
| 713 | |
| 714 | switch (channel_width) { |
| 715 | case 2: |
| 716 | dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2); |
| 717 | break; |
| 718 | default: |
| 719 | dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1); |
| 720 | break; |
| 721 | } |
| 722 | dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1)); |
| 723 | } |
| 724 | |
| 725 | temp = dram_addr->addr >> 1; |
| 726 | switch ((cen_emi_cona >> 4) & 0x3) { |
| 727 | case 0: |
| 728 | dram_addr->col = temp & 0x1FF; |
| 729 | temp = temp >> 9; |
| 730 | break; |
| 731 | case 1: |
| 732 | dram_addr->col = temp & 0x3FF; |
| 733 | temp = temp >> 10; |
| 734 | break; |
| 735 | case 2: |
| 736 | default: |
| 737 | dram_addr->col = temp & 0x7FF; |
| 738 | temp = temp >> 11; |
| 739 | break; |
| 740 | } |
| 741 | dram_addr->bk = temp & 0x7; |
| 742 | temp = temp >> 3; |
| 743 | |
| 744 | dram_addr->row = temp; |
| 745 | |
| 746 | emi_log("[EMI] ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr); |
| 747 | emi_log("[EMI] bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col); |
| 748 | } |
| 749 | |
| 750 | static unsigned int cen_emi_conh_backup = 0; |
| 751 | static unsigned int chn_emi_cona_backup = 0; |
| 752 | |
| 753 | /* return the start address of rank1 */ |
| 754 | unsigned int set_emi_before_rank1_mem_test(void) |
| 755 | { |
| 756 | cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH); |
| 757 | chn_emi_cona_backup = get_chn_emi_cona(); |
| 758 | |
| 759 | if (get_rank_nr_by_emi() == 2) { |
| 760 | /* set the rank size to 1GB for 2 channels */ |
| 761 | mt_emi_sync_write(EMI_CONH, |
| 762 | (cen_emi_conh_backup & 0x0000ffff) | 0x22220000); |
| 763 | set_chn_emi_cona( |
| 764 | (chn_emi_cona_backup & 0xff00ffff) | 0x00220000); |
| 765 | } else { |
| 766 | /* set the rank size to 1GB for 1 channel */ |
| 767 | mt_emi_sync_write(EMI_CONH, |
| 768 | (cen_emi_conh_backup & 0x0000ffff) | 0x44440000); |
| 769 | set_chn_emi_cona( |
| 770 | (chn_emi_cona_backup & 0xff00ffff) | 0x00440000); |
| 771 | } |
| 772 | |
| 773 | return 0x40000000; |
| 774 | } |
| 775 | |
| 776 | void restore_emi_after_rank1_mem_test(void) |
| 777 | { |
| 778 | mt_emi_sync_write(EMI_CONH, cen_emi_conh_backup); |
| 779 | set_chn_emi_cona(chn_emi_cona_backup); |
| 780 | } |
| 781 | |
| 782 | unsigned long long platform_memory_size(void) |
| 783 | { |
| 784 | static unsigned long long mem_size = 0; |
| 785 | int nr_rank; |
| 786 | int i; |
| 787 | unsigned long long rank_size[DRAMC_MAX_RK]; |
| 788 | |
| 789 | if (!mem_size) { |
| 790 | nr_rank = get_dram_rank_nr(); |
| 791 | |
| 792 | get_dram_rank_size(rank_size); |
| 793 | |
| 794 | for (i = 0; i < nr_rank; i++) |
| 795 | mem_size += rank_size[i]; |
| 796 | } |
| 797 | |
| 798 | return mem_size; |
| 799 | } |
| 800 | |
| 801 | size_t sdram_size(void) |
| 802 | { |
| 803 | int rank_num; |
| 804 | size_t dram_size = 0; |
| 805 | u64 rank_size[RANK_MAX]; |
| 806 | |
| 807 | get_rank_size_by_emi(rank_size); |
| 808 | rank_num = get_rank_nr_by_emi(); |
| 809 | |
| 810 | for (int i = 0; i < rank_num; i++) |
| 811 | dram_size += rank_size[i]; |
| 812 | |
| 813 | return dram_size; |
| 814 | } |