Gitiles
Code Review Sign In
review.coreboot.org / coreboot / bc3019cbd2081370ca0c556e10f923f0da6784d9 / . / src / soc / nvidia / tegra132 / Kconfig
blob: 8a5d087a7fd502801c5e8a018356aae0dd20e561 [file] [log] [blame]
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]1config SOC_NVIDIA_TEGRA132
2 bool
3 default n
4 select ARCH_BOOTBLOCK_ARMV4
Marc Jonesf5b65a32015-01-28 13:15:46 +0800[diff] [blame]5 select ARCH_VERSTAGE_ARMV4
Furquan Shaikhd42b3fc2014-06-26 00:11:29 -0700[diff] [blame]6 select ARCH_ROMSTAGE_ARMV4
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]7 select ARCH_RAMSTAGE_ARMV8_64
8 select ARM_LPAE
9 select DYNAMIC_CBMEM
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]10 select BOOTBLOCK_CONSOLE
11 select HAVE_UART_SPECIAL
12 select HAVE_UART_MEMORY_MAPPED
Furquan Shaikhd42b3fc2014-06-26 00:11:29 -0700[diff] [blame]13 select EARLY_CONSOLE
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]14 select ARM_BOOTBLOCK_CUSTOM
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]15
16if SOC_NVIDIA_TEGRA132
17
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]18config BOOTBLOCK_CPU_INIT
19 string
20 default "soc/nvidia/tegra132/bootblock.c"
21 help
22 CPU/SoC-specific bootblock code. This is useful if the
23 bootblock must load microcode or copy data from ROM before
24 searching for the bootblock.
25
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]26config BOOTBLOCK_ROM_OFFSET
27 hex
28 default 0x0
29
30config CBFS_HEADER_ROM_OFFSET
31 hex "offset of master CBFS header in ROM"
Furquan Shaikhf0990da2014-06-09 13:26:38 -0700[diff] [blame]32 default 0x40000
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]33
34config CBFS_ROM_OFFSET
35 hex "offset of CBFS data in ROM"
Furquan Shaikhf0990da2014-06-09 13:26:38 -0700[diff] [blame]36 default 0x40080
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]37
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]38config BOOTBLOCK_BASE
39 hex
40 default 0x40020000
41
42config ROMSTAGE_BASE
43 hex
44 default 0x4002c000
45
Furquan Shaikh650d11c2014-06-26 14:24:42 -0700[diff] [blame]46config SYS_SDRAM_BASE
47 hex
48 default 0x80000000
49
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]50config RAMSTAGE_BASE
51 hex
52 default 0x80200000
53
Furquan Shaikhe5d014c2014-07-07 11:45:15 -0700[diff] [blame]54config BOOTBLOCK_STACK_TOP
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]55 hex
56 default 0x40020000
57
Furquan Shaikhe5d014c2014-07-07 11:45:15 -0700[diff] [blame]58config BOOTBLOCK_STACK_BOTTOM
Furquan Shaikh732b83e2014-06-09 13:20:04 -0700[diff] [blame]59 hex
60 default 0x4001c000
61
Furquan Shaikhe5d014c2014-07-07 11:45:15 -0700[diff] [blame]62config ROMSTAGE_STACK_TOP
63 hex
64 default 0x40020000
65
66config ROMSTAGE_STACK_BOTTOM
67 hex
68 default 0x4001c000
69
70config RAMSTAGE_STACK_TOP
71 hex
72 default 0x80020000
73
74config RAMSTAGE_STACK_BOTTOM
75 hex
76 default 0x8001c000
77
Furquan Shaikhb68cb9e2014-06-25 15:19:13 -0700[diff] [blame]78config CBFS_CACHE_ADDRESS
79 hex "memory address to put CBFS cache data"
80 default 0x40006000
81
82config CBFS_CACHE_SIZE
83 hex "size of CBFS cache data"
84 default 0x00016000
85
Aaron Durbineeacf742014-07-10 15:05:13 -0500[diff] [blame]86config CONSOLE_PRERAM_BUFFER_BASE
87 hex "memory address of the CBMEM console buffer"
88 default 0x40004020
89
Aaron Durbinc13fc152014-07-14 19:13:07 -0500[diff] [blame]90config MTS_DIRECTORY
91 string "Directory where MTS microcode files are located"
92 default "3rdparty/cpu/nvidia/tegra132/current/prod"
93 help
94 Path to directory where MTS microcode files are located.
95
Aaron Durbinbc3019c2014-07-15 10:53:29 -0500[diff] [blame^]96config TRUSTZONE_CARVEOUT_SIZE_MB
97 hex "Size of Trust Zone region"
98 default 0x1
99 help
100 Size of Trust Zone area in MiB to reserve in memory map.
101
Furquan Shaikh4208e0c2014-04-28 16:43:07 -0700[diff] [blame]102endif