Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 4 | #include <cbfs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <fsp/api.h> |
| 9 | #include <fsp/ppi/mp_service_ppi.h> |
| 10 | #include <fsp/util.h> |
| 11 | #include <intelblocks/lpss.h> |
| 12 | #include <intelblocks/xdci.h> |
| 13 | #include <intelpch/lockdown.h> |
| 14 | #include <intelblocks/mp_init.h> |
| 15 | #include <soc/gpio_soc_defs.h> |
| 16 | #include <soc/intel/common/vbt.h> |
| 17 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 18 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 19 | #include <soc/ramstage.h> |
| 20 | #include <soc/soc_chip.h> |
| 21 | #include <string.h> |
| 22 | |
| 23 | /* THC assignment definition */ |
| 24 | #define THC_NONE 0 |
| 25 | #define THC_0 1 |
| 26 | #define THC_1 2 |
| 27 | |
| 28 | /* SATA DEVSLP idle timeout default values */ |
| 29 | #define DEF_DMVAL 15 |
| 30 | #define DEF_DITOVAL 625 |
| 31 | |
| 32 | /* |
| 33 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 34 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 35 | * In order to ensure that mainboard setting does not disable L1 substates |
| 36 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 37 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 38 | * value is set in fsp_params. |
| 39 | * 0: Use FSP UPD default |
| 40 | * 1: Disable L1 substates |
| 41 | * 2: Use L1.1 |
| 42 | * 3: Use L1.2 (FSP UPD default) |
| 43 | */ |
| 44 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 45 | { |
| 46 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 47 | ctl = L1_SS_L1_2; |
| 48 | return ctl - 1; |
| 49 | } |
| 50 | |
| 51 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 52 | { |
| 53 | const struct soc_intel_alderlake_config *config; |
| 54 | config = config_of_soc(); |
| 55 | |
| 56 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 57 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 58 | |
| 59 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 60 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 61 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 62 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 63 | } |
| 64 | |
| 65 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 66 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 67 | } |
| 68 | |
| 69 | static const pci_devfn_t serial_io_dev[] = { |
| 70 | PCH_DEVFN_I2C0, |
| 71 | PCH_DEVFN_I2C1, |
| 72 | PCH_DEVFN_I2C2, |
| 73 | PCH_DEVFN_I2C3, |
| 74 | PCH_DEVFN_I2C4, |
| 75 | PCH_DEVFN_I2C5, |
| 76 | PCH_DEVFN_GSPI0, |
| 77 | PCH_DEVFN_GSPI1, |
| 78 | PCH_DEVFN_GSPI2, |
| 79 | PCH_DEVFN_GSPI3, |
| 80 | PCH_DEVFN_UART0, |
| 81 | PCH_DEVFN_UART1, |
| 82 | PCH_DEVFN_UART2 |
| 83 | }; |
| 84 | |
| 85 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
| 86 | { |
| 87 | /* Override settings per board. */ |
| 88 | } |
| 89 | |
| 90 | /* UPD parameters to be initialized before SiliconInit */ |
| 91 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 92 | { |
| 93 | int i; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 94 | const struct microcode *microcode_file; |
| 95 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 96 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 97 | uint32_t enable_mask; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 98 | |
| 99 | struct device *dev; |
| 100 | struct soc_intel_alderlake_config *config; |
| 101 | config = config_of_soc(); |
| 102 | mainboard_update_soc_chip_config(config); |
| 103 | |
| 104 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 105 | parse_devicetree(params); |
| 106 | |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 107 | microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); |
| 108 | |
| 109 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 110 | /* Update CPU Microcode patch base address/size */ |
| 111 | params->MicrocodeRegionBase = (uint32_t)microcode_file; |
| 112 | params->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 113 | } |
| 114 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 115 | /* Load VBT before devicetree-specific config. */ |
| 116 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 117 | |
| 118 | /* Check if IGD is present and fill Graphics init param accordingly */ |
| 119 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 120 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); |
Ronak Kanabar | 812b54e | 2021-02-22 18:11:18 +0530 | [diff] [blame] | 121 | params->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 122 | |
| 123 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 124 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 125 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 126 | |
| 127 | /* D3Hot and D3Cold for TCSS */ |
| 128 | params->D3HotEnable = !config->TcssD3HotDisable; |
| 129 | params->D3ColdEnable = !config->TcssD3ColdDisable; |
| 130 | |
| 131 | params->TcssAuxOri = config->TcssAuxOri; |
| 132 | for (i = 0; i < 8; i++) |
| 133 | params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; |
| 134 | |
| 135 | /* |
| 136 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 137 | * evaluate this UPD value and skip sending command. There will be no |
| 138 | * delay for command completion. |
| 139 | */ |
| 140 | params->ITbtConnectTopologyTimeoutInMs = 0; |
| 141 | |
| 142 | /* Chipset Lockdown */ |
| 143 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 144 | params->PchLockDownGlobalSmi = 0; |
| 145 | params->PchLockDownBiosInterface = 0; |
| 146 | params->PchUnlockGpioPads = 1; |
| 147 | params->RtcMemoryLock = 0; |
| 148 | } else { |
| 149 | params->PchLockDownGlobalSmi = 1; |
| 150 | params->PchLockDownBiosInterface = 1; |
| 151 | params->PchUnlockGpioPads = 0; |
| 152 | params->RtcMemoryLock = 1; |
| 153 | } |
| 154 | |
| 155 | /* USB */ |
| 156 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 157 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 158 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 159 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 160 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 161 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 162 | |
| 163 | if (config->usb2_ports[i].enable) |
| 164 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 165 | else |
| 166 | params->Usb2OverCurrentPin[i] = OC_SKIP; |
| 167 | } |
| 168 | |
| 169 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 170 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 171 | if (config->usb3_ports[i].enable) |
| 172 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 173 | else |
| 174 | params->Usb3OverCurrentPin[i] = OC_SKIP; |
| 175 | |
| 176 | if (config->usb3_ports[i].tx_de_emp) { |
| 177 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 178 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 179 | } |
| 180 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 181 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 182 | params->Usb3HsioTxDownscaleAmp[i] = |
| 183 | config->usb3_ports[i].tx_downscale_amp; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 188 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
| 189 | if (dev) { |
| 190 | if (!xdci_can_enable()) |
| 191 | dev->enabled = 0; |
| 192 | params->XdciEnable = dev->enabled; |
| 193 | } else { |
| 194 | params->XdciEnable = 0; |
| 195 | } |
| 196 | |
| 197 | /* PCH UART selection for FSP Debug */ |
| 198 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 199 | ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 200 | params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
| 201 | |
| 202 | /* SATA */ |
| 203 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
| 204 | params->SataEnable = is_dev_enabled(dev); |
| 205 | if (params->SataEnable) { |
| 206 | params->SataMode = config->SataMode; |
| 207 | params->SataSalpSupport = config->SataSalpSupport; |
| 208 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 209 | sizeof(params->SataPortsEnable)); |
| 210 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 211 | sizeof(params->SataPortsDevSlp)); |
| 212 | } |
| 213 | |
| 214 | /* |
| 215 | * Power Optimizer for DMI and SATA. |
| 216 | * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |
| 217 | * Boards not needing the optimizers explicitly disables them by setting |
| 218 | * these disable variables to 1 in devicetree overrides. |
| 219 | */ |
| 220 | params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
| 221 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 222 | |
| 223 | /* |
| 224 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 225 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 226 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 227 | * The default values can be changed from devicetree. |
| 228 | */ |
| 229 | for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
| 230 | if (config->SataPortsEnableDitoConfig[i]) { |
| 231 | params->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 232 | params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | /* Enable TCPU for processor thermal control */ |
| 237 | dev = pcidev_path_on_root(SA_DEVFN_DPTF); |
| 238 | params->Device4Enable = is_dev_enabled(dev); |
| 239 | |
| 240 | /* Set TccActivationOffset */ |
| 241 | params->TccActivationOffset = config->tcc_offset; |
| 242 | |
| 243 | /* LAN */ |
| 244 | dev = pcidev_path_on_root(PCH_DEVFN_GBE); |
| 245 | params->PchLanEnable = is_dev_enabled(dev); |
| 246 | |
| 247 | /* CNVi */ |
| 248 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); |
| 249 | params->CnviMode = is_dev_enabled(dev); |
| 250 | |
| 251 | /* CNVi BT Core */ |
| 252 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_BT); |
| 253 | params->CnviBtCore = is_dev_enabled(dev); |
| 254 | |
| 255 | /* CNVi BT Audio Offload */ |
| 256 | params->CnviBtAudioOffload = config->CnviBtAudioOffload; |
| 257 | |
| 258 | /* VMD */ |
| 259 | dev = pcidev_path_on_root(SA_DEVFN_VMD); |
| 260 | params->VmdEnable = is_dev_enabled(dev); |
| 261 | |
| 262 | /* THC */ |
| 263 | dev = pcidev_path_on_root(PCH_DEVFN_THC0); |
| 264 | params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; |
| 265 | |
| 266 | dev = pcidev_path_on_root(PCH_DEVFN_THC1); |
| 267 | params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; |
| 268 | |
| 269 | /* Legacy 8254 timer support */ |
| 270 | params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 271 | params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); |
| 272 | |
| 273 | /* Enable Hybrid storage auto detection */ |
| 274 | params->HybridStorageMode = config->HybridStorageMode; |
| 275 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 276 | enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 277 | for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 278 | if (!(enable_mask & BIT(i))) |
| 279 | continue; |
| 280 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 281 | params->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 282 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 283 | params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 284 | params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 285 | params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 286 | params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 287 | } |
| 288 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 289 | params->PmSupport = 1; |
| 290 | params->Hwp = 1; |
| 291 | params->Cx = 1; |
| 292 | params->PsOnEnable = 1; |
| 293 | |
| 294 | mainboard_silicon_init_params(params); |
| 295 | } |
| 296 | |
| 297 | int soc_fsp_multi_phase_init_is_enable(void) |
| 298 | { |
| 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | /* |
| 303 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 304 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 305 | * Phase | FSP return point | Purpose |
| 306 | * ------- + ------------------------------------------------ + ------------------------------- |
| 307 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 308 | */ |
| 309 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 310 | { |
| 311 | switch (phase_index) { |
| 312 | case 1: |
| 313 | /* TCSS specific initialization here */ |
| 314 | break; |
| 315 | default: |
| 316 | break; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | /* Mainboard GPIO Configuration */ |
| 321 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 322 | { |
| 323 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 324 | } |
| 325 | |
| 326 | /* Return list of SOC LPSS controllers */ |
| 327 | const pci_devfn_t *soc_lpss_controllers_list(size_t *size) |
| 328 | { |
| 329 | *size = ARRAY_SIZE(serial_io_dev); |
| 330 | return serial_io_dev; |
| 331 | } |