Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <console/usb.h> |
| 18 | #include <bootmode.h> |
| 19 | #include <string.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <arch/cbfs.h> |
| 23 | #include <cbfs.h> |
| 24 | #include <ip_checksum.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <device/pci_def.h> |
Alexander Couzens | 81c5c76 | 2016-03-09 03:13:45 +0100 | [diff] [blame] | 27 | #include <northbridge/intel/common/mrc_cache.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 28 | #include <halt.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 29 | #include <timestamp.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 30 | #include "raminit.h" |
| 31 | #include "pei_data.h" |
| 32 | #include "sandybridge.h" |
| 33 | |
| 34 | /* Management Engine is in the southbridge */ |
| 35 | #include "southbridge/intel/bd82x6x/me.h" |
| 36 | |
| 37 | /* |
| 38 | * MRC scrambler seed offsets should be reserved in |
| 39 | * mainboard cmos.layout and not covered by checksum. |
| 40 | */ |
| 41 | #if CONFIG_USE_OPTION_TABLE |
| 42 | #include "option_table.h" |
| 43 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 44 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
| 45 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 46 | #else |
| 47 | #define CMOS_OFFSET_MRC_SEED 152 |
| 48 | #define CMOS_OFFSET_MRC_SEED_S3 156 |
| 49 | #define CMOS_OFFSET_MRC_SEED_CHK 160 |
| 50 | #endif |
| 51 | |
| 52 | void save_mrc_data(struct pei_data *pei_data) |
| 53 | { |
| 54 | u16 c1, c2, checksum; |
| 55 | struct mrc_data_container *mrcdata; |
| 56 | int output_len = ALIGN(pei_data->mrc_output_len, 16); |
| 57 | |
| 58 | /* Save the MRC S3 restore data to cbmem */ |
| 59 | mrcdata = cbmem_add |
| 60 | (CBMEM_ID_MRCDATA, |
| 61 | output_len + sizeof(struct mrc_data_container)); |
| 62 | |
| 63 | if (mrcdata != NULL) { |
| 64 | printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", |
| 65 | pei_data->mrc_output, mrcdata, output_len); |
| 66 | |
| 67 | mrcdata->mrc_signature = MRC_DATA_SIGNATURE; |
| 68 | mrcdata->mrc_data_size = output_len; |
| 69 | mrcdata->reserved = 0; |
| 70 | memcpy(mrcdata->mrc_data, pei_data->mrc_output, |
| 71 | pei_data->mrc_output_len); |
| 72 | |
| 73 | /* Zero the unused space in aligned buffer. */ |
| 74 | if (output_len > pei_data->mrc_output_len) |
| 75 | memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, |
| 76 | output_len - pei_data->mrc_output_len); |
| 77 | |
| 78 | mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, |
| 79 | mrcdata->mrc_data_size); |
| 80 | } |
| 81 | |
| 82 | /* Save the MRC seed values to CMOS */ |
| 83 | cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); |
| 84 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 85 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 86 | |
| 87 | cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); |
| 88 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 89 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 90 | |
| 91 | /* Save a simple checksum of the seed values */ |
| 92 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 93 | sizeof(u32)); |
| 94 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 95 | sizeof(u32)); |
| 96 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 97 | |
| 98 | cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 99 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); |
| 100 | } |
| 101 | |
| 102 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 103 | { |
| 104 | struct mrc_data_container *mrc_cache; |
| 105 | u16 c1, c2, checksum, seed_checksum; |
| 106 | |
| 107 | // preset just in case there is an error |
| 108 | pei_data->mrc_input = NULL; |
| 109 | pei_data->mrc_input_len = 0; |
| 110 | |
| 111 | /* Read scrambler seeds from CMOS */ |
| 112 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 113 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 114 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 115 | |
| 116 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 117 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 118 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 119 | |
| 120 | /* Compute seed checksum and compare */ |
| 121 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 122 | sizeof(u32)); |
| 123 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 124 | sizeof(u32)); |
| 125 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 126 | |
| 127 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 128 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; |
| 129 | |
| 130 | if (checksum != seed_checksum) { |
| 131 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 132 | pei_data->scrambler_seed = 0; |
| 133 | pei_data->scrambler_seed_s3 = 0; |
| 134 | return; |
| 135 | } |
| 136 | |
| 137 | if ((mrc_cache = find_current_mrc_cache()) == NULL) { |
| 138 | /* error message printed in find_current_mrc_cache */ |
| 139 | return; |
| 140 | } |
| 141 | |
| 142 | pei_data->mrc_input = mrc_cache->mrc_data; |
| 143 | pei_data->mrc_input_len = mrc_cache->mrc_data_size; |
| 144 | |
| 145 | printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", |
| 146 | __func__, pei_data->mrc_input, |
| 147 | pei_data->mrc_input_len, mrc_cache->mrc_checksum); |
| 148 | } |
| 149 | |
| 150 | static const char* ecc_decoder[] = { |
| 151 | "inactive", |
| 152 | "active on IO", |
| 153 | "disabled on IO", |
| 154 | "active" |
| 155 | }; |
| 156 | |
| 157 | /* |
| 158 | * Dump in the log memory controller configuration as read from the memory |
| 159 | * controller registers. |
| 160 | */ |
| 161 | static void report_memory_config(void) |
| 162 | { |
| 163 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 164 | int i; |
| 165 | |
| 166 | addr_decoder_common = MCHBAR32(0x5000); |
| 167 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 168 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 169 | |
| 170 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 171 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 172 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 173 | addr_decoder_common & 3, |
| 174 | (addr_decoder_common >> 2) & 3, |
| 175 | (addr_decoder_common >> 4) & 3); |
| 176 | |
| 177 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 178 | u32 ch_conf = addr_decode_ch[i]; |
| 179 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 180 | i, ch_conf); |
| 181 | printk(BIOS_DEBUG, " ECC %s\n", |
| 182 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 183 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 184 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 185 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 186 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 187 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 188 | ((ch_conf >> 0) & 0xff) * 256, |
| 189 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 190 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 191 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 192 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 193 | ((ch_conf >> 8) & 0xff) * 256, |
| 194 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 195 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 196 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 197 | } |
| 198 | } |
| 199 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 200 | /** |
| 201 | * Find PEI executable in coreboot filesystem and execute it. |
| 202 | * |
| 203 | * @param pei_data: configuration data for UEFI PEI reference code |
| 204 | */ |
| 205 | void sdram_initialize(struct pei_data *pei_data) |
| 206 | { |
| 207 | struct sys_info sysinfo; |
| 208 | int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1))); |
| 209 | |
| 210 | report_platform_info(); |
| 211 | |
| 212 | /* Wait for ME to be ready */ |
| 213 | intel_early_me_init(); |
| 214 | intel_early_me_uma_size(); |
| 215 | |
| 216 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 217 | |
| 218 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 219 | |
| 220 | sysinfo.boot_path = pei_data->boot_mode; |
| 221 | |
| 222 | /* |
| 223 | * Do not pass MRC data in for recovery mode boot, |
| 224 | * Always pass it in for S3 resume. |
| 225 | */ |
| 226 | if (!recovery_mode_enabled() || pei_data->boot_mode == 2) |
| 227 | prepare_mrc_cache(pei_data); |
| 228 | |
| 229 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 230 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
| 231 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); |
| 232 | outb(0x6, 0xcf9); |
| 233 | halt(); |
| 234 | } |
| 235 | |
| 236 | /* Pass console handler in pei_data */ |
| 237 | pei_data->tx_byte = do_putchar; |
| 238 | |
| 239 | /* Locate and call UEFI System Agent binary. */ |
| 240 | entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); |
| 241 | if (entry) { |
| 242 | int rv; |
| 243 | rv = entry (pei_data); |
| 244 | if (rv) { |
| 245 | switch (rv) { |
| 246 | case -1: |
| 247 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 248 | break; |
| 249 | case -2: |
| 250 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 251 | break; |
| 252 | default: |
| 253 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 254 | } |
| 255 | die("Nonzero MRC return value.\n"); |
| 256 | } |
| 257 | } else { |
| 258 | die("UEFI PEI System Agent not found.\n"); |
| 259 | } |
| 260 | |
| 261 | #if CONFIG_USBDEBUG_IN_ROMSTAGE |
| 262 | /* mrc.bin reconfigures USB, so reinit it to have debug */ |
| 263 | usbdebug_init(); |
| 264 | #endif |
| 265 | |
| 266 | /* For reference print the System Agent version |
| 267 | * after executing the UEFI PEI stage. |
| 268 | */ |
| 269 | u32 version = MCHBAR32(0x5034); |
| 270 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
| 271 | version >> 24 , (version >> 16) & 0xff, |
| 272 | (version >> 8) & 0xff, version & 0xff); |
| 273 | |
| 274 | /* Send ME init done for SandyBridge here. This is done |
| 275 | * inside the SystemAgent binary on IvyBridge. */ |
| 276 | if (BASE_REV_SNB == |
| 277 | (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
| 278 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 279 | else |
| 280 | intel_early_me_status(); |
| 281 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 282 | report_memory_config(); |
| 283 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 284 | |
| 285 | void perform_raminit(int s3resume) |
| 286 | { |
| 287 | int cbmem_was_initted; |
| 288 | struct pei_data pei_data; |
| 289 | |
| 290 | /* Prepare USB controller early in S3 resume */ |
| 291 | if (!mainboard_should_reset_usb(s3resume)) |
| 292 | enable_usb_bar(); |
| 293 | |
| 294 | mainboard_fill_pei_data(&pei_data); |
| 295 | |
| 296 | post_code(0x3a); |
| 297 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 298 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 299 | sdram_initialize(&pei_data); |
| 300 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 301 | if (!s3resume) |
| 302 | save_mrc_data(&pei_data); |
| 303 | |
| 304 | if (s3resume && !cbmem_was_initted) { |
| 305 | /* Failed S3 resume, reset to come up cleanly */ |
| 306 | outb(0x6, 0xcf9); |
| 307 | halt(); |
| 308 | } |
| 309 | } |