Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /** |
| 21 | * @file |
| 22 | * |
| 23 | * AMD User options selection for a Brazos platform solution system |
| 24 | * |
| 25 | * This file is placed in the user's platform directory and contains the |
| 26 | * build option selections desired for that platform. |
| 27 | * |
| 28 | * For Information about this file, see @ref platforminstall. |
| 29 | * |
| 30 | * @xrefitem bom "File Content Label" "Release Content" |
| 31 | * @e project: AGESA |
| 32 | * @e sub-project: Core |
| 33 | * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ |
| 34 | */ |
| 35 | |
| 36 | #include "AGESA.h" |
| 37 | #include "CommonReturns.h" |
| 38 | #include "Filecode.h" |
| 39 | #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE |
| 40 | |
| 41 | |
| 42 | /* Select the cpu family. */ |
| 43 | #define INSTALL_FAMILY_10_SUPPORT FALSE |
| 44 | #define INSTALL_FAMILY_12_SUPPORT FALSE |
| 45 | #define INSTALL_FAMILY_14_SUPPORT TRUE |
| 46 | #define INSTALL_FAMILY_15_SUPPORT FALSE |
| 47 | |
| 48 | /* Select the cpu socket type. */ |
| 49 | #define INSTALL_G34_SOCKET_SUPPORT FALSE |
| 50 | #define INSTALL_C32_SOCKET_SUPPORT FALSE |
| 51 | #define INSTALL_S1G3_SOCKET_SUPPORT FALSE |
| 52 | #define INSTALL_S1G4_SOCKET_SUPPORT FALSE |
| 53 | #define INSTALL_ASB2_SOCKET_SUPPORT FALSE |
| 54 | #define INSTALL_FS1_SOCKET_SUPPORT FALSE |
| 55 | #define INSTALL_FM1_SOCKET_SUPPORT FALSE |
| 56 | #define INSTALL_FP1_SOCKET_SUPPORT FALSE |
| 57 | #define INSTALL_FT1_SOCKET_SUPPORT TRUE |
| 58 | #define INSTALL_AM3_SOCKET_SUPPORT FALSE |
| 59 | |
| 60 | /* |
| 61 | * Agesa optional capabilities selection. |
| 62 | * Uncomment and mark FALSE those features you wish to include in the build. |
| 63 | * Comment out or mark TRUE those features you want to REMOVE from the build. |
| 64 | */ |
| 65 | |
| 66 | #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE |
| 67 | #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE |
| 68 | #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE |
| 69 | #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE |
| 70 | |
| 71 | #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE |
| 72 | #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE |
| 73 | #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE |
| 74 | #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE |
| 75 | #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE |
| 76 | #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE |
| 77 | #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE |
| 78 | #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE |
| 79 | #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE |
| 80 | #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE |
| 81 | |
| 82 | #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 83 | #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 84 | #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE |
| 85 | #define BLDOPT_REMOVE_ECC_SUPPORT FALSE |
| 86 | //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE |
| 87 | #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 88 | #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 89 | #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE |
| 90 | #define BLDOPT_REMOVE_DQS_TRAINING FALSE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 91 | #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 92 | #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 93 | #define BLDOPT_REMOVE_ACPI_PSTATES FALSE |
| 94 | #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE |
| 95 | #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE |
| 96 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE |
| 97 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE |
| 98 | #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE |
| 99 | #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 100 | #define BLDOPT_REMOVE_SRAT TRUE |
| 101 | #define BLDOPT_REMOVE_SLIT TRUE |
| 102 | #define BLDOPT_REMOVE_WHEA TRUE |
| 103 | #define BLDOPT_REMOVE_DMI TRUE |
| 104 | #define BLDOPT_REMOVE_HT_ASSIST TRUE |
| 105 | #define BLDOPT_REMOVE_ATM_MODE TRUE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 106 | //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE |
| 107 | //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE |
| 108 | #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE |
| 109 | //#define BLDOPT_REMOVE_C6_STATE TRUE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 110 | #define BLDOPT_REMOVE_GFX_RECOVERY TRUE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 111 | #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE |
| 112 | |
| 113 | /* |
| 114 | * Agesa entry points used in this implementation. |
| 115 | */ |
| 116 | #define AGESA_ENTRY_INIT_RESET TRUE |
| 117 | #define AGESA_ENTRY_INIT_RECOVERY FALSE |
| 118 | #define AGESA_ENTRY_INIT_EARLY TRUE |
| 119 | #define AGESA_ENTRY_INIT_POST TRUE |
| 120 | #define AGESA_ENTRY_INIT_ENV TRUE |
| 121 | #define AGESA_ENTRY_INIT_MID TRUE |
| 122 | #define AGESA_ENTRY_INIT_LATE TRUE |
| 123 | #define AGESA_ENTRY_INIT_S3SAVE TRUE |
| 124 | #define AGESA_ENTRY_INIT_RESUME TRUE |
| 125 | #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE |
Marshall Buschman | bb2ca2b | 2011-06-04 15:46:32 +0000 | [diff] [blame^] | 126 | #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Agesa configuration values selection. |
| 130 | * Uncomment and specify the value for the configuration options |
| 131 | * needed by the system. |
| 132 | */ |
| 133 | |
| 134 | /* The fixed MTRR values to be set after memory initialization. */ |
| 135 | CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = |
| 136 | { |
| 137 | { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, |
| 138 | { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, |
| 139 | { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, |
| 140 | { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E }, |
| 141 | { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E }, |
| 142 | { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E }, |
| 143 | { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E }, |
| 144 | { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E }, |
| 145 | { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E }, |
| 146 | { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E }, |
| 147 | { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E }, |
| 148 | { CPU_LIST_TERMINAL } |
| 149 | }; |
| 150 | |
| 151 | #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS |
| 152 | #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER |
| 153 | |
| 154 | #define BLDCFG_VRM_CURRENT_LIMIT 24000 |
| 155 | //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 |
| 156 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 |
| 157 | #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 |
| 158 | #define BLDCFG_VRM_SLEW_RATE 5000 |
| 159 | //#define BLDCFG_VRM_NB_SLEW_RATE 5000 |
| 160 | //#define BLDCFG_VRM_ADDITIONAL_DELAY 0 |
| 161 | //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 |
| 162 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 163 | //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE |
| 164 | #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 |
| 165 | //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 |
| 166 | |
| 167 | //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' |
| 168 | //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 169 | //#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE |
| 170 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 171 | //#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled |
| 172 | //#define BLDCFG_PLATFORM_C1E_OPDATA 0 |
| 173 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 |
| 174 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 |
| 175 | #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 |
| 176 | #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 |
| 177 | #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 |
| 178 | //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto |
| 179 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 180 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList |
| 181 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
| 182 | //#define BLDCFG_STARTING_BUSNUM 0 |
| 183 | //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 |
| 184 | //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 |
| 185 | //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 |
| 186 | //#define BLDCFG_BUID_SWAP_LIST 0 |
| 187 | //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 |
| 188 | //#define BLDCFG_HTFABRIC_LIMITS_LIST 0 |
| 189 | //#define BLDCFG_HTCHAIN_LIMITS_LIST 0 |
| 190 | //#define BLDCFG_BUS_NUMBERS_LIST 0 |
| 191 | //#define BLDCFG_IGNORE_LINK_LIST 0 |
| 192 | //#define BLDCFG_LINK_SKIP_REGANG_LIST 0 |
| 193 | //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 |
| 194 | //#define BLDCFG_USE_HT_ASSIST TRUE |
| 195 | //#define BLDCFG_USE_ATM_MODE TRUE |
| 196 | //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm |
| 197 | #define BLDCFG_S3_LATE_RESTORE FALSE |
| 198 | //#define BLDCFG_USE_32_BYTE_REFRESH FALSE |
| 199 | //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE |
| 200 | //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance |
| 201 | //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE |
| 202 | //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE |
| 203 | //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 |
| 204 | //#define BLDCFG_CFG_GNB_HD_AUDIO TRUE |
| 205 | //#define BLDCFG_CFG_ABM_SUPPORT FALSE |
| 206 | //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 |
| 207 | //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 |
| 208 | //#define BLDCFG_MEM_INIT_PSTATE 0 |
| 209 | //#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 |
| 210 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY |
| 211 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 212 | //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 213 | //#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 214 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 215 | #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE |
| 216 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE |
| 217 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE |
| 218 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE |
| 219 | #define BLDCFG_MEMORY_POWER_DOWN TRUE |
| 220 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT |
| 221 | //#define BLDCFG_ONLINE_SPARE FALSE |
| 222 | //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE |
| 223 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 224 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 225 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY |
| 226 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 227 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 228 | #define BLDCFG_USE_BURST_MODE FALSE |
| 229 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE |
| 230 | //#define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 231 | //#define BLDCFG_ECC_REDIRECTION FALSE |
| 232 | //#define BLDCFG_SCRUB_DRAM_RATE 0 |
| 233 | //#define BLDCFG_SCRUB_L2_RATE 0 |
| 234 | //#define BLDCFG_SCRUB_L3_RATE 0 |
| 235 | //#define BLDCFG_SCRUB_IC_RATE 0 |
| 236 | //#define BLDCFG_SCRUB_DC_RATE 0 |
| 237 | //#define BLDCFG_ECC_SYNC_FLOOD 0 |
| 238 | //#define BLDCFG_ECC_SYMBOL_SIZE 0 |
| 239 | //#define BLDCFG_1GB_ALIGN FALSE |
| 240 | #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO |
| 241 | #define BLDCFG_UMA_ALLOCATION_SIZE 0 |
| 242 | #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE |
| 243 | #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED |
| 244 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 245 | #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 |
| 246 | |
| 247 | /* Include the files that instantiate the configuration definitions. */ |
| 248 | #include "cpuRegisters.h" |
| 249 | #include "cpuFamRegisters.h" |
| 250 | #include "cpuFamilyTranslation.h" |
| 251 | #include "AdvancedApi.h" |
| 252 | #include "heapManager.h" |
| 253 | #include "CreateStruct.h" |
| 254 | #include "cpuFeatures.h" |
| 255 | #include "Table.h" |
| 256 | #include "CommonReturns.h" |
| 257 | #include "cpuEarlyInit.h" |
| 258 | #include "cpuLateInit.h" |
| 259 | #include "GnbInterface.h" |
| 260 | |
| 261 | /***************************************************************************** |
| 262 | * Define the RELEASE VERSION string |
| 263 | * |
| 264 | * The Release Version string should identify the next planned release. |
| 265 | * When a branch is made in preparation for a release, the release manager |
| 266 | * should change/confirm that the branch version of this file contains the |
| 267 | * string matching the desired version for the release. The trunk version of |
| 268 | * the file should always contain a trailing 'X'. This will make sure that a |
| 269 | * development build from trunk will not be confused for a released version. |
| 270 | * The release manager will need to remove the trailing 'X' and update the |
| 271 | * version string as appropriate for the release. The trunk copy of this file |
| 272 | * should also be updated/incremented for the next expected version, + trailing 'X' |
| 273 | ****************************************************************************/ |
| 274 | // This is the delivery package title, "BrazosPI" |
| 275 | // This string MUST be exactly 8 characters long |
| 276 | #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} |
| 277 | |
| 278 | // This is the release version number of the AGESA component |
| 279 | // This string MUST be exactly 12 characters long |
| 280 | #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} |
| 281 | |
| 282 | // The following definitions specify the default values for various parameters in which there are |
| 283 | // no clearly defined defaults to be used in the common file. The values below are based on product |
| 284 | // and BKDG content, please consult the AGESA Memory team for consultation. |
| 285 | #define DFLT_SCRUB_DRAM_RATE (0) |
| 286 | #define DFLT_SCRUB_L2_RATE (0) |
| 287 | #define DFLT_SCRUB_L3_RATE (0) |
| 288 | #define DFLT_SCRUB_IC_RATE (0) |
| 289 | #define DFLT_SCRUB_DC_RATE (0) |
| 290 | #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 291 | #define DFLT_VRM_SLEW_RATE (5000) |
| 292 | |
| 293 | // Instantiate all solution relevant data. |
| 294 | #include "PlatformInstall.h" |
| 295 | |
| 296 | /*---------------------------------------------------------------------------------------- |
| 297 | * CUSTOMER OVERIDES MEMORY TABLE |
| 298 | *---------------------------------------------------------------------------------------- |
| 299 | */ |
| 300 | |
| 301 | /* |
| 302 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 303 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 304 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 305 | * use its default conservative settings. |
| 306 | */ |
| 307 | CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { |
| 308 | // |
| 309 | // The following macros are supported (use comma to separate macros): |
| 310 | // |
| 311 | // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) |
| 312 | // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. |
| 313 | // AGESA will base on this value to disable unused MemClk to save power. |
| 314 | // Example: |
| 315 | // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: |
| 316 | // Bit AM3/S1g3 pin name |
| 317 | // 0 M[B,A]_CLK_H/L[0] |
| 318 | // 1 M[B,A]_CLK_H/L[1] |
| 319 | // 2 M[B,A]_CLK_H/L[2] |
| 320 | // 3 M[B,A]_CLK_H/L[3] |
| 321 | // 4 M[B,A]_CLK_H/L[4] |
| 322 | // 5 M[B,A]_CLK_H/L[5] |
| 323 | // 6 M[B,A]_CLK_H/L[6] |
| 324 | // 7 M[B,A]_CLK_H/L[7] |
| 325 | // And platform has the following routing: |
| 326 | // CS0 M[B,A]_CLK_H/L[4] |
| 327 | // CS1 M[B,A]_CLK_H/L[2] |
| 328 | // CS2 M[B,A]_CLK_H/L[3] |
| 329 | // CS3 M[B,A]_CLK_H/L[5] |
| 330 | // Then platform can specify the following macro: |
| 331 | // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) |
| 332 | // |
| 333 | // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) |
| 334 | // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. |
| 335 | // AGESA will base on this value to tristate unused CKE to save power. |
| 336 | // |
| 337 | // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) |
| 338 | // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. |
| 339 | // AGESA will base on this value to tristate unused ODT pins to save power. |
| 340 | // |
| 341 | // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) |
| 342 | // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. |
| 343 | // AGESA will base on this value to tristate unused Chip select to save power. |
| 344 | // |
| 345 | // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) |
| 346 | // Specifies the number of DIMM slots per channel. |
| 347 | // |
| 348 | // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) |
| 349 | // Specifies the number of Chip selects per channel. |
| 350 | // |
| 351 | // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) |
| 352 | // Specifies the number of channels per socket. |
| 353 | // |
| 354 | // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) |
| 355 | // Specifies DDR bus speed of channel ChannelID on socket SocketID. |
| 356 | // |
| 357 | // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) |
| 358 | // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) |
| 359 | // |
| 360 | // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, |
| 361 | // Byte6Seed, Byte7Seed, ByteEccSeed) |
| 362 | // Specifies the write leveling seed for a channel of a socket. |
| 363 | // |
| 364 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), |
| 365 | NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), |
| 366 | PSO_END |
| 367 | }; |
| 368 | |
| 369 | /* |
| 370 | * These tables are optional and may be used to adjust memory timing settings |
| 371 | */ |
| 372 | #include "mm.h" |
| 373 | #include "mn.h" |
| 374 | |
| 375 | //DA Customer table |
| 376 | CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = |
| 377 | { |
| 378 | // Hardcoded Memory Training Values |
| 379 | |
| 380 | // The following macro should be used to override training values for your platform |
| 381 | // |
| 382 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), |
| 383 | // |
| 384 | // NOTE: |
| 385 | // The following training hardcode values are example values that were taken from a tilapia motherboard |
| 386 | // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in |
| 387 | // the table and replace the byte lane values with your own. |
| 388 | // |
| 389 | // ------------------ BYTE LANES ---------------------- |
| 390 | // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC |
| 391 | // Write Data Timing |
| 392 | // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 |
| 393 | // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 |
| 394 | // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 |
| 395 | // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 |
| 396 | |
| 397 | // DQS Receiver Enable |
| 398 | // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 |
| 399 | // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 |
| 400 | // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 |
| 401 | // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 |
| 402 | |
| 403 | // Write DQS Delays |
| 404 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 |
| 405 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 |
| 406 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 |
| 407 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 |
| 408 | |
| 409 | // Read DQS Delays |
| 410 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 |
| 411 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 |
| 412 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 |
| 413 | // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 |
| 414 | //-------------------------------------------------------------------------------------------------------------------------------------------------- |
| 415 | // TABLE END |
| 416 | NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table |
| 417 | }; |
| 418 | CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); |
| 419 | |
| 420 | /* *************************************************************************** |
| 421 | * Optional User code to be included into the AGESA build |
| 422 | * These may be 32-bit call-out routines... |
| 423 | */ |
| 424 | //AGESA_STATUS |
| 425 | //AgesaReadSpd ( |
| 426 | // IN UINTN FcnData, |
| 427 | // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd |
| 428 | // ) |
| 429 | //{ |
| 430 | // /* platform code to read an SPD... */ |
| 431 | // return Status; |
| 432 | //} |
| 433 | |
| 434 | |