| Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _AMD_FW_TOOL_H_ |
| 4 | #define _AMD_FW_TOOL_H_ |
| 5 | |
| 6 | #if defined(__GLIBC__) |
| 7 | typedef unsigned long long int uint64_t; |
| 8 | typedef unsigned int uint32_t; |
| 9 | typedef unsigned char uint8_t; |
| 10 | typedef unsigned short uint16_t; |
| 11 | #endif |
| 12 | |
| 13 | |
| 14 | typedef enum _amd_fw_type { |
| 15 | AMD_FW_PSP_PUBKEY = 0, |
| 16 | AMD_FW_PSP_BOOTLOADER = 1, |
| 17 | AMD_FW_PSP_SMU_FIRMWARE = 8, |
| 18 | AMD_FW_PSP_RECOVERY = 3, |
| 19 | AMD_FW_PSP_RTM_PUBKEY = 5, |
| 20 | AMD_FW_PSP_SECURED_OS = 2, |
| 21 | AMD_FW_PSP_NVRAM = 4, |
| 22 | AMD_FW_PSP_SECURED_DEBUG = 9, |
| 23 | AMD_FW_PSP_TRUSTLETS = 12, |
| 24 | AMD_FW_PSP_TRUSTLETKEY = 13, |
| 25 | AMD_FW_PSP_SMU_FIRMWARE2 = 18, |
| 26 | AMD_PSP_FUSE_CHAIN = 11, |
| 27 | AMD_FW_PSP_SMUSCS = 95, |
| 28 | AMD_DEBUG_UNLOCK = 0x13, |
| 29 | AMD_WRAPPED_IKEK = 0x21, |
| 30 | AMD_TOKEN_UNLOCK = 0x22, |
| 31 | AMD_SEC_GASKET = 0x24, |
| 32 | AMD_MP2_FW = 0x25, |
| 33 | AMD_DRIVER_ENTRIES = 0x28, |
| 34 | AMD_S0I3_DRIVER = 0x2d, |
| 35 | AMD_ABL0 = 0x30, |
| 36 | AMD_ABL1 = 0x31, |
| 37 | AMD_ABL2 = 0x32, |
| 38 | AMD_ABL3 = 0x33, |
| 39 | AMD_ABL4 = 0x34, |
| 40 | AMD_ABL5 = 0x35, |
| 41 | AMD_ABL6 = 0x36, |
| 42 | AMD_ABL7 = 0x37, |
| 43 | AMD_FW_PSP_WHITELIST = 0x3a, |
| 44 | AMD_FW_L2_PTR = 0x40, |
| 45 | AMD_FW_PSP_VERSTAGE = 0x52, |
| 46 | AMD_FW_VERSTAGE_SIG = 0x53, |
| 47 | AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ |
| 48 | AMD_FW_GEC, |
| 49 | AMD_FW_XHCI, |
| 50 | AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ |
| 51 | AMD_FW_SKIP /* This is for non-applicable options. */ |
| 52 | } amd_fw_type; |
| 53 | |
| 54 | typedef enum _amd_bios_type { |
| 55 | AMD_BIOS_APCB = 0x60, |
| 56 | AMD_BIOS_APOB = 0x61, |
| 57 | AMD_BIOS_BIN = 0x62, |
| 58 | AMD_BIOS_APOB_NV = 0x63, |
| 59 | AMD_BIOS_PMUI = 0x64, |
| 60 | AMD_BIOS_PMUD = 0x65, |
| 61 | AMD_BIOS_UCODE = 0x66, |
| 62 | AMD_BIOS_APCB_BK = 0x68, |
| 63 | AMD_BIOS_MP2_CFG = 0x6a, |
| 64 | AMD_BIOS_PSP_SHARED_MEM = 0x6b, |
| 65 | AMD_BIOS_L2_PTR = 0x70, |
| 66 | AMD_BIOS_INVALID, |
| 67 | AMD_BIOS_SKIP |
| 68 | } amd_bios_type; |
| 69 | |
| 70 | |
| 71 | #define BDT_LVL1 0x1 |
| 72 | #define BDT_LVL2 0x2 |
| 73 | #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) |
| 74 | typedef struct _amd_bios_entry { |
| 75 | amd_bios_type type; |
| 76 | char *filename; |
| 77 | int subpr; |
| 78 | int region_type; |
| 79 | int reset; |
| 80 | int copy; |
| 81 | int ro; |
| 82 | int zlib; |
| 83 | int inst; |
| 84 | uint64_t src; |
| 85 | uint64_t dest; |
| 86 | size_t size; |
| 87 | int level; |
| 88 | } amd_bios_entry; |
| 89 | |
| 90 | |
| 91 | #define PSP_LVL1 0x1 |
| 92 | #define PSP_LVL2 0x2 |
| 93 | #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) |
| 94 | typedef struct _amd_fw_entry { |
| 95 | amd_fw_type type; |
| 96 | char *filename; |
| 97 | uint8_t subprog; |
| 98 | int level; |
| 99 | uint64_t other; |
| 100 | } amd_fw_entry; |
| 101 | |
| 102 | typedef struct _amd_cb_config { |
| 103 | uint8_t have_whitelist; |
| 104 | uint8_t unlock_secure; |
| 105 | uint8_t use_secureos; |
| 106 | uint8_t load_mp2_fw; |
| 107 | uint8_t s0i3; |
| 108 | } amd_cb_config; |
| 109 | |
| 110 | void register_fw_fuse(char *str); |
| 111 | uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps); |
| 112 | |
| 113 | #define OK 0 |
| 114 | |
| 115 | #define LINE_EOF (1) |
| 116 | #define LINE_TOO_LONG (2) |
| 117 | |
| 118 | |
| 119 | #endif /* _AMD_FW_TOOL_H_ */ |