| Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Gabe Black | 3c7e939 | 2013-05-26 07:15:57 -0700 | [diff] [blame] | 2 | |
| Sam Lewis | ad7b2e2 | 2020-08-03 20:18:29 +1000 | [diff] [blame] | 3 | #ifndef __SOC_TI_AM335X_DMTIMER_H__ |
| 4 | #define __SOC_TI_AM335X_DMTIMER_H__ |
| Gabe Black | 3c7e939 | 2013-05-26 07:15:57 -0700 | [diff] [blame] | 5 | |
| 6 | #include <stdint.h> |
| 7 | |
| Sam Lewis | fde084b | 2020-08-04 19:47:50 +1000 | [diff] [blame] | 8 | #define M_OSC_MHZ (24) |
| Gabe Black | 3c7e939 | 2013-05-26 07:15:57 -0700 | [diff] [blame] | 9 | |
| Sam Lewis | fde084b | 2020-08-04 19:47:50 +1000 | [diff] [blame] | 10 | struct am335x_dmtimer { |
| 11 | uint32_t tidr; |
| 12 | uint8_t res1[12]; |
| 13 | uint32_t tiocp_cfg; |
| 14 | uint8_t res2[12]; |
| 15 | uint32_t irq_eoi; |
| 16 | uint32_t irqstatus_raw; |
| 17 | uint32_t irqstatus; |
| 18 | uint32_t irqenable_set; |
| 19 | uint32_t irqenable_clr; |
| 20 | uint32_t irqwakeen; |
| 21 | uint32_t tclr; |
| 22 | uint32_t tcrr; |
| 23 | uint32_t tldr; |
| 24 | uint32_t ttgr; |
| 25 | uint32_t twps; |
| 26 | uint32_t tmar; |
| 27 | uint32_t tcar1; |
| 28 | uint32_t tsicr; |
| 29 | uint32_t tcar2; |
| 30 | }; |
| 31 | |
| 32 | #define TCLR_ST (0x01 << 0) |
| 33 | #define TCLR_AR (0x01 << 1) |
| 34 | |
| 35 | #define DMTIMER_2 (0x48040000) |
| Gabe Black | 3c7e939 | 2013-05-26 07:15:57 -0700 | [diff] [blame] | 36 | |
| 37 | #endif |