Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 5 | #include <delay.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 6 | #include <soc/dp.h> |
| 7 | #include <soc/fimd.h> |
| 8 | #include <soc/i2c.h> |
| 9 | #include <soc/power.h> |
| 10 | #include <soc/sysreg.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 11 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 12 | /* FIXME: I think the DP controller shouldn't be hardcoded here... */ |
| 13 | static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE; |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 14 | |
| 15 | /* for debugging, it's nice to get control on a per-file basis. |
| 16 | * I had a bit of a discussion with myself (boring!) about |
| 17 | * how to do this and for the moment this is the easiest way. |
| 18 | * These debugging statements allowed me to find the final bugs. |
| 19 | */ |
| 20 | |
| 21 | #if 0 |
| 22 | static inline void fwadl(unsigned long l,void *v) { |
| 23 | writel(l, v); |
| 24 | printk(BIOS_SPEW, "W %p %p\n", v, (void *)l); |
| 25 | } |
| 26 | #define lwrite32(a,b) fwadl((unsigned long)(a), (void *)(b)) |
| 27 | |
| 28 | static inline unsigned long fradl(void *v) { |
| 29 | unsigned long l = readl(v); |
| 30 | printk(BIOS_SPEW, "R %p %p\n", v, (void *)l); |
| 31 | return l; |
| 32 | } |
| 33 | |
| 34 | #define lread32(a) fradl((void *)(a)) |
| 35 | #else |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 36 | #define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 37 | #define lread32(a) read32((void *)(a)) |
| 38 | #endif |
| 39 | |
| 40 | static void exynos_dp_enable_video_input(u32 enable) |
| 41 | { |
| 42 | u32 reg; |
| 43 | |
| 44 | reg = lread32(&dp_regs->video_ctl1); |
| 45 | reg &= ~VIDEO_EN_MASK; |
| 46 | |
| 47 | /* enable video input*/ |
| 48 | if (enable) |
| 49 | reg |= VIDEO_EN_MASK; |
| 50 | |
| 51 | lwrite32(reg, &dp_regs->video_ctl1); |
| 52 | |
| 53 | return; |
| 54 | } |
| 55 | |
| 56 | void exynos_dp_disable_video_bist(void) |
| 57 | { |
| 58 | u32 reg; |
| 59 | reg = lread32(&dp_regs->video_ctl4); |
| 60 | reg &= ~VIDEO_BIST_MASK; |
| 61 | lwrite32(reg, &dp_regs->video_ctl4); |
| 62 | } |
| 63 | |
| 64 | void exynos_dp_enable_video_mute(unsigned int enable) |
| 65 | { |
| 66 | u32 reg; |
| 67 | |
| 68 | reg = lread32(&dp_regs->video_ctl1); |
| 69 | reg &= ~(VIDEO_MUTE_MASK); |
| 70 | if (enable) |
| 71 | reg |= VIDEO_MUTE_MASK; |
| 72 | |
| 73 | lwrite32(reg, &dp_regs->video_ctl1); |
| 74 | |
| 75 | return; |
| 76 | } |
| 77 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 78 | static void exynos_dp_init_analog_param(void) |
| 79 | { |
| 80 | u32 reg; |
| 81 | |
| 82 | /* |
| 83 | * Set termination |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 84 | * Normal bandgap, Normal swing, Tx terminal resistor 61 ohm |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 85 | * 24M Phy clock, TX digital logic power is 100:1.0625V |
| 86 | */ |
| 87 | reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM | |
| 88 | SWING_A_30PER_G_NORMAL; |
| 89 | lwrite32(reg, &dp_regs->analog_ctl1); |
| 90 | |
| 91 | reg = SEL_24M | TX_DVDD_BIT_1_0625V; |
| 92 | lwrite32(reg, &dp_regs->analog_ctl2); |
| 93 | |
| 94 | /* |
| 95 | * Set power source for internal clk driver to 1.0625v. |
| 96 | * Select current reference of TX driver current to 00:Ipp/2+Ic/2. |
| 97 | * Set VCO range of PLL +- 0uA |
| 98 | */ |
| 99 | reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO; |
| 100 | lwrite32(reg, &dp_regs->analog_ctl3); |
| 101 | |
| 102 | /* |
| 103 | * Set AUX TX terminal resistor to 102 ohm |
| 104 | * Set AUX channel amplitude control |
| 105 | */ |
| 106 | reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; |
| 107 | lwrite32(reg, &dp_regs->pll_filter_ctl1); |
| 108 | |
| 109 | /* |
| 110 | * PLL loop filter bandwidth |
| 111 | * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz |
| 112 | * PLL digital power select: 1.2500V |
| 113 | */ |
| 114 | reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV; |
| 115 | |
| 116 | lwrite32(reg, &dp_regs->amp_tuning_ctl); |
| 117 | |
| 118 | /* |
| 119 | * PLL loop filter bandwidth |
| 120 | * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz |
| 121 | * PLL digital power select: 1.1250V |
| 122 | */ |
| 123 | reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V; |
| 124 | lwrite32(reg, &dp_regs->pll_ctl); |
| 125 | } |
| 126 | |
| 127 | static void exynos_dp_init_interrupt(void) |
| 128 | { |
| 129 | /* Set interrupt registers to initial states */ |
| 130 | |
| 131 | /* |
| 132 | * Disable interrupt |
| 133 | * INT pin assertion polarity. It must be configured |
| 134 | * correctly according to ICU setting. |
| 135 | * 1 = assert high, 0 = assert low |
| 136 | */ |
| 137 | lwrite32(INT_POL, &dp_regs->int_ctl); |
| 138 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 139 | /* Clear pending registers */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 140 | lwrite32(0xff, &dp_regs->common_int_sta1); |
| 141 | lwrite32(0xff, &dp_regs->common_int_sta2); |
| 142 | lwrite32(0xff, &dp_regs->common_int_sta3); |
| 143 | lwrite32(0xff, &dp_regs->common_int_sta4); |
| 144 | lwrite32(0xff, &dp_regs->int_sta); |
| 145 | |
| 146 | /* 0:mask,1: unmask */ |
| 147 | lwrite32(0x00, &dp_regs->int_sta_mask1); |
| 148 | lwrite32(0x00, &dp_regs->int_sta_mask2); |
| 149 | lwrite32(0x00, &dp_regs->int_sta_mask3); |
| 150 | lwrite32(0x00, &dp_regs->int_sta_mask4); |
| 151 | lwrite32(0x00, &dp_regs->int_sta_mask); |
| 152 | } |
| 153 | |
| 154 | void exynos_dp_reset(void) |
| 155 | { |
| 156 | u32 reg_func_1; |
| 157 | |
| 158 | /*dp tx sw reset*/ |
| 159 | lwrite32(RESET_DP_TX, &dp_regs->tx_sw_reset); |
| 160 | |
| 161 | exynos_dp_enable_video_input(DP_DISABLE); |
| 162 | exynos_dp_disable_video_bist(); |
| 163 | exynos_dp_enable_video_mute(DP_DISABLE); |
| 164 | |
| 165 | /* software reset */ |
| 166 | reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | |
| 167 | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | |
| 168 | HDCP_FUNC_EN_N | SW_FUNC_EN_N; |
| 169 | |
| 170 | lwrite32(reg_func_1, &dp_regs->func_en1); |
| 171 | lwrite32(reg_func_1, &dp_regs->func_en2); |
| 172 | |
| 173 | mdelay(1); |
| 174 | |
| 175 | exynos_dp_init_analog_param(); |
| 176 | exynos_dp_init_interrupt(); |
| 177 | |
| 178 | return; |
| 179 | } |
| 180 | |
| 181 | void exynos_dp_enable_sw_func(unsigned int enable) |
| 182 | { |
| 183 | u32 reg; |
| 184 | |
| 185 | reg = lread32(&dp_regs->func_en1); |
| 186 | reg &= ~(SW_FUNC_EN_N); |
| 187 | |
| 188 | if (!enable) |
| 189 | reg |= SW_FUNC_EN_N; |
| 190 | |
| 191 | lwrite32(reg, &dp_regs->func_en1); |
| 192 | |
| 193 | return; |
| 194 | } |
| 195 | |
| 196 | unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) |
| 197 | { |
| 198 | u32 reg; |
| 199 | |
| 200 | reg = lread32(&dp_regs->phy_pd); |
| 201 | switch (block) { |
| 202 | case AUX_BLOCK: |
| 203 | reg &= ~(AUX_PD); |
| 204 | if (enable) |
| 205 | reg |= AUX_PD; |
| 206 | break; |
| 207 | case CH0_BLOCK: |
| 208 | reg &= ~(CH0_PD); |
| 209 | if (enable) |
| 210 | reg |= CH0_PD; |
| 211 | break; |
| 212 | case CH1_BLOCK: |
| 213 | reg &= ~(CH1_PD); |
| 214 | if (enable) |
| 215 | reg |= CH1_PD; |
| 216 | break; |
| 217 | case CH2_BLOCK: |
| 218 | reg &= ~(CH2_PD); |
| 219 | if (enable) |
| 220 | reg |= CH2_PD; |
| 221 | break; |
| 222 | case CH3_BLOCK: |
| 223 | reg &= ~(CH3_PD); |
| 224 | if (enable) |
| 225 | reg |= CH3_PD; |
| 226 | break; |
| 227 | case ANALOG_TOTAL: |
| 228 | reg &= ~PHY_PD; |
| 229 | if (enable) |
| 230 | reg |= PHY_PD; |
| 231 | break; |
| 232 | case POWER_ALL: |
| 233 | reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD | |
| 234 | CH3_PD); |
| 235 | if (enable) |
| 236 | reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD | |
| 237 | CH2_PD | CH3_PD); |
| 238 | break; |
| 239 | default: |
| 240 | printk(BIOS_ERR, "DP undefined block number : %d\n", block); |
| 241 | return -1; |
| 242 | } |
| 243 | |
| 244 | lwrite32(reg, &dp_regs->phy_pd); |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | unsigned int exynos_dp_get_pll_lock_status(void) |
| 250 | { |
| 251 | u32 reg; |
| 252 | |
| 253 | reg = lread32(&dp_regs->debug_ctl); |
| 254 | |
| 255 | if (reg & PLL_LOCK) |
| 256 | return PLL_LOCKED; |
| 257 | else |
| 258 | return PLL_UNLOCKED; |
| 259 | } |
| 260 | |
| 261 | static void exynos_dp_set_pll_power(unsigned int enable) |
| 262 | { |
| 263 | u32 reg; |
| 264 | |
| 265 | reg = lread32(&dp_regs->pll_ctl); |
| 266 | reg &= ~(DP_PLL_PD); |
| 267 | |
| 268 | if (!enable) |
| 269 | reg |= DP_PLL_PD; |
| 270 | |
| 271 | lwrite32(reg, &dp_regs->pll_ctl); |
| 272 | } |
| 273 | |
| 274 | int exynos_dp_init_analog_func(void) |
| 275 | { |
| 276 | int ret = EXYNOS_DP_SUCCESS; |
| 277 | unsigned int retry_cnt = 10; |
| 278 | u32 reg; |
| 279 | |
| 280 | /*Power On All Analog block */ |
| 281 | exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); |
| 282 | |
| 283 | reg = PLL_LOCK_CHG; |
| 284 | lwrite32(reg, &dp_regs->common_int_sta1); |
| 285 | |
| 286 | reg = lread32(&dp_regs->debug_ctl); |
| 287 | reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); |
| 288 | lwrite32(reg, &dp_regs->debug_ctl); |
| 289 | |
| 290 | /*Assert DP PLL Reset*/ |
| 291 | reg = lread32(&dp_regs->pll_ctl); |
| 292 | reg |= DP_PLL_RESET; |
| 293 | lwrite32(reg, &dp_regs->pll_ctl); |
| 294 | |
| 295 | mdelay(1); |
| 296 | |
| 297 | /*Deassert DP PLL Reset*/ |
| 298 | reg = lread32(&dp_regs->pll_ctl); |
| 299 | reg &= ~(DP_PLL_RESET); |
| 300 | lwrite32(reg, &dp_regs->pll_ctl); |
| 301 | |
| 302 | exynos_dp_set_pll_power(DP_ENABLE); |
| 303 | |
| 304 | while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) { |
| 305 | mdelay(1); |
| 306 | retry_cnt--; |
| 307 | if (retry_cnt == 0) { |
| 308 | printk(BIOS_ERR, "DP dp's pll lock failed : retry : %d\n", |
| 309 | retry_cnt); |
| 310 | return -1; |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | printk(BIOS_DEBUG, "dp's pll lock success(%d)\n", retry_cnt); |
| 315 | |
| 316 | /* Enable Serdes FIFO function and Link symbol clock domain module */ |
| 317 | reg = lread32(&dp_regs->func_en2); |
| 318 | reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N |
| 319 | | AUX_FUNC_EN_N); |
| 320 | lwrite32(reg, &dp_regs->func_en2); |
| 321 | |
| 322 | return ret; |
| 323 | } |
| 324 | |
| 325 | void exynos_dp_init_hpd(void) |
| 326 | { |
| 327 | u32 reg; |
| 328 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 329 | /* Clear interrupts related to Hot Plug Detect */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 330 | reg = HOTPLUG_CHG | HPD_LOST | PLUG; |
| 331 | lwrite32(reg, &dp_regs->common_int_sta4); |
| 332 | |
| 333 | reg = INT_HPD; |
| 334 | lwrite32(reg, &dp_regs->int_sta); |
| 335 | |
| 336 | reg = lread32(&dp_regs->sys_ctl3); |
| 337 | reg &= ~(F_HPD | HPD_CTRL); |
| 338 | lwrite32(reg, &dp_regs->sys_ctl3); |
| 339 | |
| 340 | return; |
| 341 | } |
| 342 | |
| 343 | static inline void exynos_dp_reset_aux(void) |
| 344 | { |
| 345 | u32 reg; |
| 346 | |
| 347 | /* Disable AUX channel module */ |
| 348 | reg = lread32(&dp_regs->func_en2); |
| 349 | reg |= AUX_FUNC_EN_N; |
| 350 | lwrite32(reg, &dp_regs->func_en2); |
| 351 | |
| 352 | return; |
| 353 | } |
| 354 | |
| 355 | void exynos_dp_init_aux(void) |
| 356 | { |
| 357 | u32 reg; |
| 358 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 359 | /* Clear interrupts related to AUX channel */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 360 | reg = RPLY_RECEIV | AUX_ERR; |
| 361 | lwrite32(reg, &dp_regs->int_sta); |
| 362 | |
| 363 | exynos_dp_reset_aux(); |
| 364 | |
| 365 | /* Disable AUX transaction H/W retry */ |
| 366 | reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)| |
| 367 | AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; |
| 368 | lwrite32(reg, &dp_regs->aux_hw_retry_ctl); |
| 369 | |
| 370 | /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ |
| 371 | reg = DEFER_CTRL_EN | DEFER_COUNT(1); |
| 372 | lwrite32(reg, &dp_regs->aux_ch_defer_ctl); |
| 373 | |
| 374 | /* Enable AUX channel module */ |
| 375 | reg = lread32(&dp_regs->func_en2); |
| 376 | reg &= ~AUX_FUNC_EN_N; |
| 377 | lwrite32(reg, &dp_regs->func_en2); |
| 378 | |
| 379 | return; |
| 380 | } |
| 381 | |
| 382 | void exynos_dp_config_interrupt(void) |
| 383 | { |
| 384 | u32 reg; |
| 385 | |
| 386 | /* 0: mask, 1: unmask */ |
| 387 | reg = COMMON_INT_MASK_1; |
| 388 | lwrite32(reg, &dp_regs->common_int_mask1); |
| 389 | |
| 390 | reg = COMMON_INT_MASK_2; |
| 391 | lwrite32(reg, &dp_regs->common_int_mask2); |
| 392 | |
| 393 | reg = COMMON_INT_MASK_3; |
| 394 | lwrite32(reg, &dp_regs->common_int_mask3); |
| 395 | |
| 396 | reg = COMMON_INT_MASK_4; |
| 397 | lwrite32(reg, &dp_regs->common_int_mask4); |
| 398 | |
| 399 | reg = INT_STA_MASK; |
| 400 | lwrite32(reg, &dp_regs->int_sta_mask); |
| 401 | |
| 402 | return; |
| 403 | } |
| 404 | |
| 405 | unsigned int exynos_dp_get_plug_in_status(void) |
| 406 | { |
| 407 | u32 reg; |
| 408 | |
| 409 | reg = lread32(&dp_regs->sys_ctl3); |
| 410 | if (reg & HPD_STATUS) |
| 411 | return 0; |
| 412 | |
| 413 | return -1; |
| 414 | } |
| 415 | |
| 416 | unsigned int exynos_dp_detect_hpd(void) |
| 417 | { |
| 418 | int timeout_loop = DP_TIMEOUT_LOOP_COUNT; |
| 419 | |
| 420 | mdelay(2); |
| 421 | |
| 422 | while (exynos_dp_get_plug_in_status() != 0) { |
| 423 | if (timeout_loop == 0) |
| 424 | return -1; |
Ronald G. Minnich | bc6cc11 | 2013-08-16 19:53:41 -0700 | [diff] [blame] | 425 | mdelay(1); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 426 | timeout_loop--; |
| 427 | } |
| 428 | |
| 429 | return EXYNOS_DP_SUCCESS; |
| 430 | } |
| 431 | |
| 432 | unsigned int exynos_dp_start_aux_transaction(void) |
| 433 | { |
| 434 | u32 reg; |
| 435 | unsigned int ret = 0; |
| 436 | unsigned int retry_cnt; |
| 437 | |
| 438 | /* Enable AUX CH operation */ |
| 439 | reg = lread32(&dp_regs->aux_ch_ctl2); |
| 440 | reg |= AUX_EN; |
| 441 | lwrite32(reg, &dp_regs->aux_ch_ctl2); |
| 442 | |
| 443 | retry_cnt = 10; |
| 444 | while (retry_cnt) { |
| 445 | reg = lread32(&dp_regs->int_sta); |
| 446 | if (!(reg & RPLY_RECEIV)) { |
| 447 | if (retry_cnt == 0) { |
| 448 | printk(BIOS_ERR, "DP Reply Timeout!!\n"); |
| 449 | ret = -1; |
| 450 | return ret; |
| 451 | } |
| 452 | mdelay(1); |
| 453 | retry_cnt--; |
| 454 | } else |
| 455 | break; |
| 456 | } |
| 457 | |
| 458 | /* Clear interrupt source for AUX CH command reply */ |
| 459 | lwrite32(reg, &dp_regs->int_sta); |
| 460 | |
| 461 | /* Clear interrupt source for AUX CH access error */ |
| 462 | reg = lread32(&dp_regs->int_sta); |
| 463 | if (reg & AUX_ERR) { |
| 464 | printk(BIOS_ERR, "DP Aux Access Error\n"); |
| 465 | lwrite32(AUX_ERR, &dp_regs->int_sta); |
| 466 | ret = -1; |
| 467 | return ret; |
| 468 | } |
| 469 | |
| 470 | /* Check AUX CH error access status */ |
| 471 | reg = lread32(&dp_regs->aux_ch_sta); |
| 472 | if ((reg & AUX_STATUS_MASK) != 0) { |
| 473 | printk(BIOS_DEBUG, "DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK); |
| 474 | ret = -1; |
| 475 | return ret; |
| 476 | } |
| 477 | return EXYNOS_DP_SUCCESS; |
| 478 | } |
| 479 | |
| 480 | unsigned int exynos_dp_write_byte_to_dpcd(u32 reg_addr, u8 data) |
| 481 | { |
| 482 | u32 reg; |
| 483 | unsigned int ret; |
| 484 | |
| 485 | /* Clear AUX CH data buffer */ |
| 486 | reg = BUF_CLR; |
| 487 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 488 | |
| 489 | /* Select DPCD device address */ |
| 490 | reg = AUX_ADDR_7_0(reg_addr); |
| 491 | lwrite32(reg, &dp_regs->aux_addr_7_0); |
| 492 | reg = AUX_ADDR_15_8(reg_addr); |
| 493 | lwrite32(reg, &dp_regs->aux_addr_15_8); |
| 494 | reg = AUX_ADDR_19_16(reg_addr); |
| 495 | lwrite32(reg, &dp_regs->aux_addr_19_16); |
| 496 | |
| 497 | /* Write data buffer */ |
| 498 | reg = data; |
| 499 | lwrite32(reg, &dp_regs->buf_data0); |
| 500 | |
| 501 | /* |
| 502 | * Set DisplayPort transaction and write 1 byte |
| 503 | * If bit 3 is 1, DisplayPort transaction. |
| 504 | * If Bit 3 is 0, I2C transaction. |
| 505 | */ |
| 506 | reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; |
| 507 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 508 | |
| 509 | /* Start AUX transaction */ |
| 510 | ret = exynos_dp_start_aux_transaction(); |
| 511 | if (ret != EXYNOS_DP_SUCCESS) { |
| 512 | printk(BIOS_ERR, "DP Aux transaction failed\n"); |
| 513 | } |
| 514 | |
| 515 | return ret; |
| 516 | } |
| 517 | |
| 518 | unsigned int exynos_dp_read_byte_from_dpcd(u32 reg_addr, |
| 519 | unsigned char *data) |
| 520 | { |
| 521 | u32 reg; |
| 522 | int retval; |
| 523 | |
| 524 | /* Clear AUX CH data buffer */ |
| 525 | reg = BUF_CLR; |
| 526 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 527 | |
| 528 | /* Select DPCD device address */ |
| 529 | reg = AUX_ADDR_7_0(reg_addr); |
| 530 | lwrite32(reg, &dp_regs->aux_addr_7_0); |
| 531 | reg = AUX_ADDR_15_8(reg_addr); |
| 532 | lwrite32(reg, &dp_regs->aux_addr_15_8); |
| 533 | reg = AUX_ADDR_19_16(reg_addr); |
| 534 | lwrite32(reg, &dp_regs->aux_addr_19_16); |
| 535 | |
| 536 | /* |
| 537 | * Set DisplayPort transaction and read 1 byte |
| 538 | * If bit 3 is 1, DisplayPort transaction. |
| 539 | * If Bit 3 is 0, I2C transaction. |
| 540 | */ |
| 541 | reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; |
| 542 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 543 | |
| 544 | /* Start AUX transaction */ |
| 545 | retval = exynos_dp_start_aux_transaction(); |
| 546 | if (retval != EXYNOS_DP_SUCCESS) |
| 547 | printk(BIOS_DEBUG, "DP Aux Transaction fail!\n"); |
| 548 | |
| 549 | /* Read data buffer */ |
| 550 | reg = lread32(&dp_regs->buf_data0); |
| 551 | *data = (unsigned char)(reg & 0xff); |
| 552 | |
| 553 | return retval; |
| 554 | } |
| 555 | |
| 556 | unsigned int exynos_dp_write_bytes_to_dpcd(u32 reg_addr, |
| 557 | unsigned int count, |
| 558 | unsigned char data[]) |
| 559 | { |
| 560 | u32 reg; |
| 561 | unsigned int start_offset; |
| 562 | unsigned int cur_data_count; |
| 563 | unsigned int cur_data_idx; |
| 564 | unsigned int retry_cnt; |
| 565 | unsigned int ret = 0; |
| 566 | |
| 567 | /* Clear AUX CH data buffer */ |
| 568 | reg = BUF_CLR; |
| 569 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 570 | |
| 571 | start_offset = 0; |
| 572 | while (start_offset < count) { |
| 573 | /* Buffer size of AUX CH is 16 * 4bytes */ |
| 574 | if ((count - start_offset) > 16) |
| 575 | cur_data_count = 16; |
| 576 | else |
| 577 | cur_data_count = count - start_offset; |
| 578 | |
| 579 | retry_cnt = 5; |
| 580 | while (retry_cnt) { |
| 581 | /* Select DPCD device address */ |
| 582 | reg = AUX_ADDR_7_0(reg_addr + start_offset); |
| 583 | lwrite32(reg, &dp_regs->aux_addr_7_0); |
| 584 | reg = AUX_ADDR_15_8(reg_addr + start_offset); |
| 585 | lwrite32(reg, &dp_regs->aux_addr_15_8); |
| 586 | reg = AUX_ADDR_19_16(reg_addr + start_offset); |
| 587 | lwrite32(reg, &dp_regs->aux_addr_19_16); |
| 588 | |
| 589 | for (cur_data_idx = 0; cur_data_idx < cur_data_count; |
| 590 | cur_data_idx++) { |
| 591 | reg = data[start_offset + cur_data_idx]; |
| 592 | lwrite32(reg, (void *)((unsigned int)&dp_regs->buf_data0 + |
| 593 | (4 * cur_data_idx))); |
| 594 | } |
| 595 | /* |
| 596 | * Set DisplayPort transaction and write |
| 597 | * If bit 3 is 1, DisplayPort transaction. |
| 598 | * If Bit 3 is 0, I2C transaction. |
| 599 | */ |
| 600 | reg = AUX_LENGTH(cur_data_count) | |
| 601 | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; |
| 602 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 603 | |
| 604 | /* Start AUX transaction */ |
| 605 | ret = exynos_dp_start_aux_transaction(); |
| 606 | if (ret != EXYNOS_DP_SUCCESS) { |
| 607 | if (retry_cnt == 0) { |
| 608 | printk(BIOS_ERR, "DP Aux Transaction failed\n"); |
| 609 | return ret; |
| 610 | } |
| 611 | retry_cnt--; |
| 612 | } else |
| 613 | break; |
| 614 | } |
| 615 | start_offset += cur_data_count; |
| 616 | } |
| 617 | |
| 618 | return ret; |
| 619 | } |
| 620 | |
| 621 | unsigned int exynos_dp_read_bytes_from_dpcd(u32 reg_addr, |
| 622 | unsigned int count, |
| 623 | unsigned char data[]) |
| 624 | { |
| 625 | u32 reg; |
| 626 | unsigned int start_offset; |
| 627 | unsigned int cur_data_count; |
| 628 | unsigned int cur_data_idx; |
| 629 | unsigned int retry_cnt; |
| 630 | unsigned int ret = 0; |
| 631 | |
| 632 | /* Clear AUX CH data buffer */ |
| 633 | reg = BUF_CLR; |
| 634 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 635 | |
| 636 | start_offset = 0; |
| 637 | while (start_offset < count) { |
| 638 | /* Buffer size of AUX CH is 16 * 4bytes */ |
| 639 | if ((count - start_offset) > 16) |
| 640 | cur_data_count = 16; |
| 641 | else |
| 642 | cur_data_count = count - start_offset; |
| 643 | |
| 644 | retry_cnt = 5; |
| 645 | while (retry_cnt) { |
| 646 | /* Select DPCD device address */ |
| 647 | reg = AUX_ADDR_7_0(reg_addr + start_offset); |
| 648 | lwrite32(reg, &dp_regs->aux_addr_7_0); |
| 649 | reg = AUX_ADDR_15_8(reg_addr + start_offset); |
| 650 | lwrite32(reg, &dp_regs->aux_addr_15_8); |
| 651 | reg = AUX_ADDR_19_16(reg_addr + start_offset); |
| 652 | lwrite32(reg, &dp_regs->aux_addr_19_16); |
| 653 | /* |
| 654 | * Set DisplayPort transaction and read |
| 655 | * If bit 3 is 1, DisplayPort transaction. |
| 656 | * If Bit 3 is 0, I2C transaction. |
| 657 | */ |
| 658 | reg = AUX_LENGTH(cur_data_count) | |
| 659 | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; |
| 660 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 661 | |
| 662 | /* Start AUX transaction */ |
| 663 | ret = exynos_dp_start_aux_transaction(); |
| 664 | if (ret != EXYNOS_DP_SUCCESS) { |
| 665 | if (retry_cnt == 0) { |
| 666 | printk(BIOS_ERR, "DP Aux Transaction failed\n"); |
| 667 | return ret; |
| 668 | } |
| 669 | retry_cnt--; |
| 670 | } else |
| 671 | break; |
| 672 | } |
| 673 | |
| 674 | for (cur_data_idx = 0; cur_data_idx < cur_data_count; |
| 675 | cur_data_idx++) { |
| 676 | reg = lread32((void *)((u32)&dp_regs->buf_data0 + |
| 677 | 4 * cur_data_idx)); |
| 678 | data[start_offset + cur_data_idx] = (unsigned char)reg; |
| 679 | } |
| 680 | |
| 681 | start_offset += cur_data_count; |
| 682 | } |
| 683 | |
| 684 | return ret; |
| 685 | } |
| 686 | |
| 687 | int exynos_dp_select_i2c_device(u32 device_addr, |
| 688 | u32 reg_addr) |
| 689 | { |
| 690 | u32 reg; |
| 691 | int retval; |
| 692 | |
| 693 | /* Set EDID device address */ |
| 694 | reg = device_addr; |
| 695 | lwrite32(reg, &dp_regs->aux_addr_7_0); |
| 696 | lwrite32(0x0, &dp_regs->aux_addr_15_8); |
| 697 | lwrite32(0x0, &dp_regs->aux_addr_19_16); |
| 698 | |
| 699 | /* Set offset from base address of EDID device */ |
| 700 | lwrite32(reg_addr, &dp_regs->buf_data0); |
| 701 | |
| 702 | /* |
| 703 | * Set I2C transaction and write address |
| 704 | * If bit 3 is 1, DisplayPort transaction. |
| 705 | * If Bit 3 is 0, I2C transaction. |
| 706 | */ |
| 707 | reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | |
| 708 | AUX_TX_COMM_WRITE; |
| 709 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 710 | |
| 711 | /* Start AUX transaction */ |
| 712 | retval = exynos_dp_start_aux_transaction(); |
| 713 | if (retval != 0) |
| 714 | printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__); |
| 715 | |
| 716 | return retval; |
| 717 | } |
| 718 | |
| 719 | int exynos_dp_read_byte_from_i2c(u32 device_addr, |
| 720 | u32 reg_addr, |
| 721 | unsigned int *data) |
| 722 | { |
| 723 | u32 reg; |
| 724 | int i; |
| 725 | int retval; |
| 726 | |
| 727 | for (i = 0; i < 10; i++) { |
| 728 | /* Clear AUX CH data buffer */ |
| 729 | reg = BUF_CLR; |
| 730 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 731 | |
| 732 | /* Select EDID device */ |
| 733 | retval = exynos_dp_select_i2c_device(device_addr, reg_addr); |
| 734 | if (retval != 0) { |
| 735 | printk(BIOS_DEBUG, "DP Select EDID device fail. retry !\n"); |
| 736 | continue; |
| 737 | } |
| 738 | |
| 739 | /* |
| 740 | * Set I2C transaction and read data |
| 741 | * If bit 3 is 1, DisplayPort transaction. |
| 742 | * If Bit 3 is 0, I2C transaction. |
| 743 | */ |
| 744 | reg = AUX_TX_COMM_I2C_TRANSACTION | |
| 745 | AUX_TX_COMM_READ; |
| 746 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 747 | |
| 748 | /* Start AUX transaction */ |
| 749 | retval = exynos_dp_start_aux_transaction(); |
| 750 | if (retval != EXYNOS_DP_SUCCESS) |
| 751 | printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__); |
| 752 | } |
| 753 | |
| 754 | /* Read data */ |
| 755 | if (retval == 0) |
| 756 | *data = lread32(&dp_regs->buf_data0); |
| 757 | |
| 758 | return retval; |
| 759 | } |
| 760 | |
| 761 | int exynos_dp_read_bytes_from_i2c(u32 device_addr, |
| 762 | u32 reg_addr, unsigned int count, unsigned char edid[]) |
| 763 | { |
| 764 | u32 reg; |
| 765 | unsigned int i, j; |
| 766 | unsigned int cur_data_idx; |
| 767 | unsigned int defer = 0; |
| 768 | int retval = 0; |
| 769 | |
| 770 | for (i = 0; i < count; i += 16) { /* use 16 burst */ |
| 771 | for (j = 0; j < 100; j++) { |
| 772 | /* Clear AUX CH data buffer */ |
| 773 | reg = BUF_CLR; |
| 774 | lwrite32(reg, &dp_regs->buffer_data_ctl); |
| 775 | |
| 776 | /* Set normal AUX CH command */ |
| 777 | reg = lread32(&dp_regs->aux_ch_ctl2); |
| 778 | reg &= ~ADDR_ONLY; |
| 779 | lwrite32(reg, &dp_regs->aux_ch_ctl2); |
| 780 | |
| 781 | /* |
| 782 | * If Rx sends defer, Tx sends only reads |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 783 | * request without sending address |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 784 | */ |
| 785 | if (!defer) |
| 786 | retval = |
| 787 | exynos_dp_select_i2c_device(device_addr, |
| 788 | reg_addr + i); |
| 789 | else |
| 790 | defer = 0; |
| 791 | |
| 792 | if (retval == EXYNOS_DP_SUCCESS) { |
| 793 | /* |
| 794 | * Set I2C transaction and write data |
| 795 | * If bit 3 is 1, DisplayPort transaction. |
| 796 | * If Bit 3 is 0, I2C transaction. |
| 797 | */ |
| 798 | reg = AUX_LENGTH(16) | |
| 799 | AUX_TX_COMM_I2C_TRANSACTION | |
| 800 | AUX_TX_COMM_READ; |
| 801 | lwrite32(reg, &dp_regs->aux_ch_ctl1); |
| 802 | |
| 803 | /* Start AUX transaction */ |
| 804 | retval = exynos_dp_start_aux_transaction(); |
| 805 | if (retval == 0) |
| 806 | break; |
| 807 | else |
| 808 | printk(BIOS_ERR, "DP Aux Transaction fail!\n"); |
| 809 | } |
| 810 | /* Check if Rx sends defer */ |
| 811 | reg = lread32(&dp_regs->aux_rx_comm); |
| 812 | if (reg == AUX_RX_COMM_AUX_DEFER || |
| 813 | reg == AUX_RX_COMM_I2C_DEFER) { |
| 814 | printk(BIOS_ERR, "DP Defer: %d\n\n", reg); |
| 815 | defer = 1; |
| 816 | } |
| 817 | } |
| 818 | |
| 819 | for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { |
| 820 | reg = lread32((void *)((u32)&dp_regs->buf_data0 |
| 821 | + 4 * cur_data_idx)); |
| 822 | edid[i + cur_data_idx] = (unsigned char)reg; |
| 823 | } |
| 824 | } |
| 825 | |
| 826 | return retval; |
| 827 | } |
| 828 | |
| 829 | void exynos_dp_reset_macro(void) |
| 830 | { |
| 831 | u32 reg; |
| 832 | |
| 833 | reg = lread32(&dp_regs->phy_test); |
| 834 | reg |= MACRO_RST; |
| 835 | lwrite32(reg, &dp_regs->phy_test); |
| 836 | |
| 837 | /* 10 us is the minimum Macro reset time. */ |
Ronald G. Minnich | bc6cc11 | 2013-08-16 19:53:41 -0700 | [diff] [blame] | 838 | udelay(50); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 839 | |
| 840 | reg &= ~MACRO_RST; |
| 841 | lwrite32(reg, &dp_regs->phy_test); |
| 842 | } |
| 843 | |
| 844 | void exynos_dp_set_link_bandwidth(unsigned char bwtype) |
| 845 | { |
| 846 | u32 reg; |
| 847 | |
| 848 | reg = (u32)bwtype; |
| 849 | |
| 850 | /* Set bandwidth to 2.7G or 1.62G */ |
| 851 | if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70)) |
| 852 | lwrite32(reg, &dp_regs->link_bw_set); |
| 853 | } |
| 854 | |
| 855 | unsigned char exynos_dp_get_link_bandwidth(void) |
| 856 | { |
| 857 | unsigned char ret; |
| 858 | u32 reg; |
| 859 | |
| 860 | reg = lread32(&dp_regs->link_bw_set); |
| 861 | ret = (unsigned char)reg; |
| 862 | |
| 863 | return ret; |
| 864 | } |
| 865 | |
| 866 | void exynos_dp_set_lane_count(unsigned char count) |
| 867 | { |
| 868 | u32 reg; |
| 869 | |
| 870 | reg = (u32)count; |
| 871 | |
| 872 | if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) || |
| 873 | (count == DP_LANE_CNT_4)) |
| 874 | lwrite32(reg, &dp_regs->lane_count_set); |
| 875 | } |
| 876 | |
| 877 | unsigned int exynos_dp_get_lane_count(void) |
| 878 | { |
| 879 | u32 reg; |
| 880 | |
| 881 | reg = lread32(&dp_regs->lane_count_set); |
| 882 | |
| 883 | return reg; |
| 884 | } |
| 885 | |
| 886 | unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt) |
| 887 | { |
| 888 | void *reg_list[DP_LANE_CNT_4] = { |
| 889 | &dp_regs->ln0_link_training_ctl, |
| 890 | &dp_regs->ln1_link_training_ctl, |
| 891 | &dp_regs->ln2_link_training_ctl, |
| 892 | &dp_regs->ln3_link_training_ctl, |
| 893 | }; |
| 894 | |
| 895 | return lread32(reg_list[lanecnt]); |
| 896 | } |
| 897 | |
| 898 | void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, |
| 899 | unsigned char lanecnt) |
| 900 | { |
Elyes HAOUAS | 39303d5 | 2018-07-08 12:40:45 +0200 | [diff] [blame] | 901 | void *reg_list[DP_LANE_CNT_4] = { |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 902 | &dp_regs->ln0_link_training_ctl, |
| 903 | &dp_regs->ln1_link_training_ctl, |
| 904 | &dp_regs->ln2_link_training_ctl, |
| 905 | &dp_regs->ln3_link_training_ctl, |
| 906 | }; |
| 907 | |
| 908 | lwrite32(request_val, reg_list[lanecnt]); |
| 909 | } |
| 910 | |
| 911 | void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt) |
| 912 | { |
| 913 | unsigned char i; |
| 914 | u32 reg; |
| 915 | void *reg_list[DP_LANE_CNT_4] = { |
| 916 | &dp_regs->ln0_link_training_ctl, |
| 917 | &dp_regs->ln1_link_training_ctl, |
| 918 | &dp_regs->ln2_link_training_ctl, |
| 919 | &dp_regs->ln3_link_training_ctl, |
| 920 | }; |
| 921 | u32 reg_shift[DP_LANE_CNT_4] = { |
| 922 | PRE_EMPHASIS_SET_0_SHIFT, |
| 923 | PRE_EMPHASIS_SET_1_SHIFT, |
| 924 | PRE_EMPHASIS_SET_2_SHIFT, |
| 925 | PRE_EMPHASIS_SET_3_SHIFT |
| 926 | }; |
| 927 | |
| 928 | for (i = 0; i < lanecnt; i++) { |
| 929 | reg = level << reg_shift[i]; |
| 930 | lwrite32(reg, reg_list[i]); |
| 931 | } |
| 932 | } |
| 933 | |
| 934 | void exynos_dp_set_training_pattern(unsigned int pattern) |
| 935 | { |
| 936 | u32 reg = 0; |
| 937 | |
| 938 | switch (pattern) { |
| 939 | case PRBS7: |
| 940 | reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; |
| 941 | break; |
| 942 | case D10_2: |
| 943 | reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; |
| 944 | break; |
| 945 | case TRAINING_PTN1: |
| 946 | reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; |
| 947 | break; |
| 948 | case TRAINING_PTN2: |
| 949 | reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; |
| 950 | break; |
| 951 | case DP_NONE: |
| 952 | reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE | |
| 953 | SW_TRAINING_PATTERN_SET_NORMAL; |
| 954 | break; |
| 955 | default: |
| 956 | break; |
| 957 | } |
| 958 | |
| 959 | lwrite32(reg, &dp_regs->training_ptn_set); |
| 960 | } |
| 961 | |
| 962 | void exynos_dp_enable_enhanced_mode(unsigned char enable) |
| 963 | { |
| 964 | u32 reg; |
| 965 | |
| 966 | reg = lread32(&dp_regs->sys_ctl4); |
| 967 | reg &= ~ENHANCED; |
| 968 | |
| 969 | if (enable) |
| 970 | reg |= ENHANCED; |
| 971 | |
| 972 | lwrite32(reg, &dp_regs->sys_ctl4); |
| 973 | } |
| 974 | |
| 975 | void exynos_dp_enable_scrambling(unsigned int enable) |
| 976 | { |
| 977 | u32 reg; |
| 978 | |
| 979 | reg = lread32(&dp_regs->training_ptn_set); |
| 980 | reg &= ~(SCRAMBLING_DISABLE); |
| 981 | |
| 982 | if (!enable) |
| 983 | reg |= SCRAMBLING_DISABLE; |
| 984 | |
| 985 | lwrite32(reg, &dp_regs->training_ptn_set); |
| 986 | } |
| 987 | int exynos_dp_init_video(void) |
| 988 | { |
| 989 | unsigned int reg; |
| 990 | |
| 991 | /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */ |
| 992 | reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; |
| 993 | lwrite32(reg, &dp_regs->common_int_sta1); |
| 994 | |
| 995 | /* I_STRM__CLK detect : DE_CTL : Auto detect */ |
| 996 | reg &= ~DET_CTRL; |
| 997 | lwrite32(reg, &dp_regs->sys_ctl1); |
| 998 | return 0; |
| 999 | } |
| 1000 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 1001 | void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) |
| 1002 | { |
| 1003 | u32 reg; |
| 1004 | |
| 1005 | /* Video Slave mode setting */ |
| 1006 | reg = lread32(&dp_regs->func_en1); |
| 1007 | reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); |
| 1008 | reg |= MASTER_VID_FUNC_EN_N; |
| 1009 | lwrite32(reg, &dp_regs->func_en1); |
| 1010 | |
| 1011 | /* Configure Interlaced for slave mode video */ |
| 1012 | reg = lread32(&dp_regs->video_ctl10); |
| 1013 | reg &= ~INTERACE_SCAN_CFG; |
| 1014 | reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT); |
| 1015 | printk(BIOS_SPEW, "interlaced %d\n", video_info->interlaced); |
| 1016 | lwrite32(reg, &dp_regs->video_ctl10); |
| 1017 | |
| 1018 | /* Configure V sync polarity for slave mode video */ |
| 1019 | reg = lread32(&dp_regs->video_ctl10); |
| 1020 | reg &= ~VSYNC_POLARITY_CFG; |
| 1021 | reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT); |
| 1022 | lwrite32(reg, &dp_regs->video_ctl10); |
| 1023 | |
| 1024 | /* Configure H sync polarity for slave mode video */ |
| 1025 | reg = lread32(&dp_regs->video_ctl10); |
| 1026 | reg &= ~HSYNC_POLARITY_CFG; |
| 1027 | reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); |
| 1028 | lwrite32(reg, &dp_regs->video_ctl10); |
| 1029 | |
| 1030 | /*Set video mode to slave mode */ |
| 1031 | reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; |
| 1032 | lwrite32(reg, &dp_regs->soc_general_ctl); |
| 1033 | } |
| 1034 | |
| 1035 | void exynos_dp_set_video_color_format(struct edp_video_info *video_info) |
| 1036 | { |
| 1037 | u32 reg; |
| 1038 | |
| 1039 | /* Configure the input color depth, color space, dynamic range */ |
| 1040 | reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) | |
| 1041 | (video_info->color_depth << IN_BPC_SHIFT) | |
| 1042 | (video_info->color_space << IN_COLOR_F_SHIFT); |
| 1043 | lwrite32(reg, &dp_regs->video_ctl2); |
| 1044 | |
| 1045 | /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ |
| 1046 | reg = lread32(&dp_regs->video_ctl3); |
| 1047 | reg &= ~IN_YC_COEFFI_MASK; |
| 1048 | if (video_info->ycbcr_coeff) |
| 1049 | reg |= IN_YC_COEFFI_ITU709; |
| 1050 | else |
| 1051 | reg |= IN_YC_COEFFI_ITU601; |
| 1052 | lwrite32(reg, &dp_regs->video_ctl3); |
| 1053 | } |
| 1054 | |
| 1055 | unsigned int exynos_dp_is_slave_video_stream_clock_on(void) |
| 1056 | { |
| 1057 | u32 reg; |
| 1058 | |
| 1059 | /* Update Video stream clk detect status */ |
| 1060 | reg = lread32(&dp_regs->sys_ctl1); |
| 1061 | lwrite32(reg, &dp_regs->sys_ctl1); |
| 1062 | |
| 1063 | reg = lread32(&dp_regs->sys_ctl1); |
| 1064 | |
| 1065 | if (!(reg & DET_STA)) { |
| 1066 | printk(BIOS_DEBUG, "DP Input stream clock not detected.\n"); |
| 1067 | return -1; |
| 1068 | } |
| 1069 | |
| 1070 | return EXYNOS_DP_SUCCESS; |
| 1071 | } |
| 1072 | |
| 1073 | void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, |
| 1074 | unsigned int n_value) |
| 1075 | { |
| 1076 | u32 reg; |
| 1077 | |
| 1078 | if (type == REGISTER_M) { |
| 1079 | reg = lread32(&dp_regs->sys_ctl4); |
| 1080 | reg |= FIX_M_VID; |
| 1081 | lwrite32(reg, &dp_regs->sys_ctl4); |
| 1082 | reg = M_VID0_CFG(m_value); |
| 1083 | lwrite32(reg, &dp_regs->m_vid0); |
| 1084 | reg = M_VID1_CFG(m_value); |
| 1085 | lwrite32(reg, &dp_regs->m_vid1); |
| 1086 | reg = M_VID2_CFG(m_value); |
| 1087 | lwrite32(reg, &dp_regs->m_vid2); |
| 1088 | |
| 1089 | reg = N_VID0_CFG(n_value); |
| 1090 | lwrite32(reg, &dp_regs->n_vid0); |
| 1091 | reg = N_VID1_CFG(n_value); |
| 1092 | lwrite32(reg, &dp_regs->n_vid1); |
| 1093 | reg = N_VID2_CFG(n_value); |
| 1094 | lwrite32(reg, &dp_regs->n_vid2); |
| 1095 | } else { |
| 1096 | reg = lread32(&dp_regs->sys_ctl4); |
| 1097 | reg &= ~FIX_M_VID; |
| 1098 | lwrite32(reg, &dp_regs->sys_ctl4); |
| 1099 | } |
| 1100 | } |
| 1101 | |
| 1102 | void exynos_dp_set_video_timing_mode(unsigned int type) |
| 1103 | { |
| 1104 | u32 reg; |
| 1105 | |
| 1106 | reg = lread32(&dp_regs->video_ctl10); |
| 1107 | reg &= ~FORMAT_SEL; |
| 1108 | |
| 1109 | if (type != VIDEO_TIMING_FROM_CAPTURE) |
| 1110 | reg |= FORMAT_SEL; |
| 1111 | |
| 1112 | lwrite32(reg, &dp_regs->video_ctl10); |
| 1113 | } |
| 1114 | |
| 1115 | void exynos_dp_enable_video_master(unsigned int enable) |
| 1116 | { |
| 1117 | u32 reg; |
| 1118 | |
| 1119 | reg = lread32(&dp_regs->soc_general_ctl); |
| 1120 | if (enable) { |
| 1121 | reg &= ~VIDEO_MODE_MASK; |
| 1122 | reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; |
| 1123 | } else { |
| 1124 | reg &= ~VIDEO_MODE_MASK; |
| 1125 | reg |= VIDEO_MODE_SLAVE_MODE; |
| 1126 | } |
| 1127 | |
| 1128 | lwrite32(reg, &dp_regs->soc_general_ctl); |
| 1129 | } |
| 1130 | |
| 1131 | void exynos_dp_start_video(void) |
| 1132 | { |
| 1133 | u32 reg; |
| 1134 | |
| 1135 | /* Enable Video input and disable Mute */ |
| 1136 | reg = lread32(&dp_regs->video_ctl1); |
| 1137 | reg |= VIDEO_EN; |
| 1138 | lwrite32(reg, &dp_regs->video_ctl1); |
| 1139 | } |
| 1140 | |
| 1141 | unsigned int exynos_dp_is_video_stream_on(void) |
| 1142 | { |
| 1143 | u32 reg; |
| 1144 | |
| 1145 | /* Update STRM_VALID */ |
| 1146 | reg = lread32(&dp_regs->sys_ctl3); |
| 1147 | lwrite32(reg, &dp_regs->sys_ctl3); |
| 1148 | |
| 1149 | reg = lread32(&dp_regs->sys_ctl3); |
| 1150 | |
| 1151 | if (!(reg & STRM_VALID)) |
| 1152 | return -1; |
| 1153 | |
| 1154 | return EXYNOS_DP_SUCCESS; |
| 1155 | } |
| 1156 | |
| 1157 | void dp_phy_control(unsigned int enable) |
| 1158 | { |
| 1159 | u32 cfg; |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 1160 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 1161 | cfg = lread32(&exynos_power->dptx_phy_control); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 1162 | if (enable) |
| 1163 | cfg |= EXYNOS_DP_PHY_ENABLE; |
| 1164 | else |
| 1165 | cfg &= ~EXYNOS_DP_PHY_ENABLE; |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 1166 | lwrite32(cfg, &exynos_power->dptx_phy_control); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 1167 | } |