Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 2 | |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <delay.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 5 | #include <soc/dp.h> |
| 6 | #include <soc/fimd.h> |
| 7 | #include <soc/i2c.h> |
| 8 | #include <soc/power.h> |
| 9 | #include <soc/sysreg.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 10 | #include <string.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 11 | |
| 12 | /* |
| 13 | * Here is the rough outline of how we bring up the display: |
| 14 | * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD |
| 15 | * 2. Source determines video mode by reading DPCD receiver capability field |
| 16 | * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD |
| 17 | * 0000Dh). |
| 18 | * 3. Sink replies DPCD receiver capability field. |
| 19 | * 4. Source starts EDID read thru I2C-over-AUX. |
| 20 | * 5. Sink replies EDID thru I2C-over-AUX. |
| 21 | * 6. Source determines link configuration, such as MAX_LINK_RATE and |
| 22 | * MAX_LANE_COUNT. Source also determines which type of eDP Authentication |
| 23 | * method to use and writes DPCD link configuration field (DPCD 00100h to |
| 24 | * 0010Ah) including eDP configuration set (DPCD 0010Ah). |
| 25 | * 7. Source starts link training. Sink does clock recovery and equalization. |
| 26 | * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). |
| 27 | * 9. Sink replies DPCD link status field. If main link is not stable, Source |
| 28 | * repeats Step 7. |
| 29 | * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video |
| 30 | * parameters and recovers stream clock. |
| 31 | * 11. Source sends video data. |
| 32 | */ |
| 33 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 34 | static int exynos_dp_init_dp(void) |
| 35 | { |
| 36 | int ret; |
| 37 | exynos_dp_reset(); |
| 38 | |
| 39 | /* SW defined function Normal operation */ |
| 40 | exynos_dp_enable_sw_func(DP_ENABLE); |
| 41 | |
| 42 | ret = exynos_dp_init_analog_func(); |
| 43 | if (ret != EXYNOS_DP_SUCCESS) |
| 44 | return ret; |
| 45 | |
| 46 | exynos_dp_init_hpd(); |
| 47 | exynos_dp_init_aux(); |
| 48 | |
| 49 | return ret; |
| 50 | } |
| 51 | |
| 52 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) |
| 53 | { |
| 54 | int i; |
| 55 | unsigned char sum = 0; |
| 56 | |
| 57 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) |
| 58 | sum = sum + edid_data[i]; |
| 59 | |
| 60 | return sum; |
| 61 | } |
| 62 | |
| 63 | static unsigned int exynos_dp_read_edid(void) |
| 64 | { |
| 65 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; |
| 66 | unsigned int extend_block = 0; |
| 67 | unsigned char sum; |
| 68 | unsigned char test_vector; |
| 69 | int retval = 0; |
| 70 | |
| 71 | /* |
| 72 | * EDID device address is 0x50. |
| 73 | * However, if necessary, you must have set upper address |
| 74 | * into E-EDID in I2C device, 0x30. |
| 75 | */ |
| 76 | |
| 77 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ |
| 78 | if (exynos_dp_read_byte_from_i2c |
| 79 | (I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, &extend_block)) |
| 80 | return -1; |
| 81 | |
| 82 | if (extend_block > 0) { |
| 83 | /* Read EDID data */ |
| 84 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 85 | EDID_HEADER_PATTERN, |
| 86 | EDID_BLOCK_LENGTH, |
| 87 | &edid[EDID_HEADER_PATTERN]); |
| 88 | |
| 89 | if (retval != 0) { |
| 90 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 91 | return -1; |
| 92 | } |
| 93 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 94 | if (sum != 0) { |
| 95 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 96 | return -1; |
| 97 | } |
| 98 | /* Read additional EDID data */ |
| 99 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 100 | EDID_BLOCK_LENGTH, |
| 101 | EDID_BLOCK_LENGTH, |
| 102 | &edid[EDID_BLOCK_LENGTH]); |
| 103 | if (retval != 0) { |
| 104 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 105 | return -1; |
| 106 | } |
| 107 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); |
| 108 | if (sum != 0) { |
| 109 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 110 | return -1; |
| 111 | } |
| 112 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, |
| 113 | &test_vector); |
| 114 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 115 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, |
| 116 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
| 117 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, |
| 118 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 119 | } |
| 120 | } else { |
| 121 | /* Read EDID data */ |
| 122 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 123 | EDID_HEADER_PATTERN, |
| 124 | EDID_BLOCK_LENGTH, |
| 125 | &edid[EDID_HEADER_PATTERN]); |
| 126 | |
| 127 | if (retval != 0) { |
| 128 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 129 | return -1; |
| 130 | } |
| 131 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 132 | if (sum != 0) { |
| 133 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 134 | return -1; |
| 135 | } |
| 136 | |
| 137 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, |
| 138 | &test_vector); |
| 139 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 140 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, |
| 141 | edid[EDID_CHECKSUM]); |
| 142 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, |
| 143 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 144 | } |
| 145 | |
| 146 | } |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info) |
| 152 | { |
| 153 | unsigned char buf[12]; |
| 154 | unsigned int ret; |
| 155 | unsigned char temp; |
| 156 | unsigned char retry_cnt; |
| 157 | unsigned char dpcd_rev[16]; |
| 158 | unsigned char lane_bw[16]; |
| 159 | unsigned char lane_cnt[16]; |
| 160 | |
| 161 | memset(dpcd_rev, 0, sizeof(dpcd_rev)); |
| 162 | memset(lane_bw, 0, sizeof(lane_bw)); |
| 163 | memset(lane_cnt, 0, sizeof(lane_cnt)); |
| 164 | memset(buf, 0, sizeof(buf)); |
| 165 | |
| 166 | retry_cnt = 5; |
| 167 | while (retry_cnt) { |
| 168 | /* Read DPCD 0x0000-0x000b */ |
| 169 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12, |
| 170 | buf); |
| 171 | if (ret != EXYNOS_DP_SUCCESS) { |
| 172 | if (retry_cnt == 0) { |
| 173 | printk(BIOS_ERR, "DP read_byte_from_dpcd() failed\n"); |
| 174 | return ret; |
| 175 | } |
| 176 | retry_cnt--; |
| 177 | } else |
| 178 | break; |
| 179 | } |
| 180 | /* */ |
| 181 | temp = buf[DPCD_DPCD_REV]; |
| 182 | if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) |
| 183 | edp_info->dpcd_rev = temp; |
| 184 | else { |
| 185 | printk(BIOS_ERR, "DP Wrong DPCD Rev : %x\n", temp); |
| 186 | return -1; |
| 187 | } |
| 188 | temp = buf[DPCD_MAX_LINK_RATE]; |
| 189 | if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) |
| 190 | edp_info->lane_bw = temp; |
| 191 | else { |
| 192 | printk(BIOS_ERR, "DP Wrong MAX LINK RATE : %x\n", temp); |
| 193 | return -1; |
| 194 | } |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 195 | /*Refer VESA Display Port Standard Ver1.1a Page 120 */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 196 | if (edp_info->dpcd_rev == DP_DPCD_REV_11) { |
| 197 | temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; |
| 198 | if (buf[DPCD_MAX_LANE_COUNT] & 0x80) |
| 199 | edp_info->dpcd_efc = 1; |
| 200 | else |
| 201 | edp_info->dpcd_efc = 0; |
| 202 | } else { |
| 203 | temp = buf[DPCD_MAX_LANE_COUNT]; |
| 204 | edp_info->dpcd_efc = 0; |
| 205 | } |
| 206 | |
| 207 | if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || |
| 208 | temp == DP_LANE_CNT_4) { |
| 209 | edp_info->lane_cnt = temp; |
| 210 | } else { |
| 211 | printk(BIOS_ERR, "DP Wrong MAX LANE COUNT : %x\n", temp); |
| 212 | return -1; |
| 213 | } |
| 214 | |
Ronald G. Minnich | 71e1c83 | 2013-08-27 14:06:19 -0700 | [diff] [blame] | 215 | if (edp_info->raw_edid){ |
| 216 | ret = EXYNOS_DP_SUCCESS; |
| 217 | printk(BIOS_SPEW, "EDID compiled in, skipping read\n"); |
| 218 | } else { |
| 219 | ret = exynos_dp_read_edid(); |
| 220 | if (ret != EXYNOS_DP_SUCCESS) { |
| 221 | printk(BIOS_ERR, "DP exynos_dp_read_edid() failed\n"); |
| 222 | return -1; |
| 223 | } |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | return ret; |
| 227 | } |
| 228 | |
| 229 | static void exynos_dp_init_training(void) |
| 230 | { |
| 231 | /* |
| 232 | * MACRO_RST must be applied after the PLL_LOCK to avoid |
| 233 | * the DP inter pair skew issue for at least 10 us |
| 234 | */ |
| 235 | exynos_dp_reset_macro(); |
| 236 | |
| 237 | /* All DP analog module power up */ |
| 238 | exynos_dp_set_analog_power_down(POWER_ALL, 0); |
| 239 | } |
| 240 | |
| 241 | static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info) |
| 242 | { |
| 243 | unsigned char buf[5]; |
| 244 | unsigned int ret; |
| 245 | |
| 246 | edp_info->lt_info.lt_status = DP_LT_CR; |
| 247 | edp_info->lt_info.ep_loop = 0; |
| 248 | edp_info->lt_info.cr_loop[0] = 0; |
| 249 | edp_info->lt_info.cr_loop[1] = 0; |
| 250 | edp_info->lt_info.cr_loop[2] = 0; |
| 251 | edp_info->lt_info.cr_loop[3] = 0; |
| 252 | |
| 253 | /* Set sink to D0 (Sink Not Ready) mode. */ |
| 254 | ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE, |
| 255 | DPCD_SET_POWER_STATE_D0); |
| 256 | if (ret != EXYNOS_DP_SUCCESS) { |
| 257 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 258 | return ret; |
| 259 | } |
| 260 | |
| 261 | /* Set link rate and count as you want to establish*/ |
| 262 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); |
| 263 | exynos_dp_set_lane_count(edp_info->lane_cnt); |
| 264 | |
| 265 | /* Setup RX configuration */ |
| 266 | buf[0] = edp_info->lane_bw; |
| 267 | buf[1] = edp_info->lane_cnt; |
| 268 | |
| 269 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2, |
| 270 | buf); |
| 271 | if (ret != EXYNOS_DP_SUCCESS) { |
| 272 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 273 | return ret; |
| 274 | } |
| 275 | |
| 276 | exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0, |
| 277 | edp_info->lane_cnt); |
| 278 | |
| 279 | /* Set training pattern 1 */ |
| 280 | exynos_dp_set_training_pattern(TRAINING_PTN1); |
| 281 | |
| 282 | /* Set RX training pattern */ |
| 283 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; |
| 284 | |
| 285 | buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 286 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 287 | buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 288 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 289 | buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 290 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 291 | buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 292 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 293 | |
| 294 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 295 | 5, buf); |
| 296 | if (ret != EXYNOS_DP_SUCCESS) { |
| 297 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 298 | return ret; |
| 299 | } |
| 300 | return ret; |
| 301 | } |
| 302 | |
| 303 | static unsigned int exynos_dp_training_pattern_dis(void) |
| 304 | { |
| 305 | unsigned int ret; |
| 306 | |
| 307 | exynos_dp_set_training_pattern(DP_NONE); |
| 308 | |
| 309 | ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 310 | DPCD_TRAINING_PATTERN_DISABLED); |
| 311 | if (ret != EXYNOS_DP_SUCCESS) { |
| 312 | printk(BIOS_ERR, "DP requst_link_traninig_req failed\n"); |
| 313 | return -1; |
| 314 | } |
| 315 | |
| 316 | return ret; |
| 317 | } |
| 318 | |
| 319 | static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) |
| 320 | { |
| 321 | unsigned char data; |
| 322 | unsigned int ret; |
| 323 | |
| 324 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET, |
| 325 | &data); |
| 326 | if (ret != EXYNOS_DP_SUCCESS) { |
| 327 | printk(BIOS_ERR, "DP read_from_dpcd failed\n"); |
| 328 | return -1; |
| 329 | } |
| 330 | |
| 331 | if (enable) |
| 332 | data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); |
| 333 | else |
| 334 | data = DPCD_LN_COUNT_SET(data); |
| 335 | |
| 336 | ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, |
| 337 | data); |
| 338 | if (ret != EXYNOS_DP_SUCCESS) { |
| 339 | printk(BIOS_ERR, "DP write_to_dpcd failed\n"); |
| 340 | return -1; |
| 341 | |
| 342 | } |
| 343 | |
| 344 | return ret; |
| 345 | } |
| 346 | |
| 347 | static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode) |
| 348 | { |
| 349 | unsigned int ret; |
| 350 | |
| 351 | ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode); |
| 352 | if (ret != EXYNOS_DP_SUCCESS) { |
| 353 | printk(BIOS_ERR, "DP rx_enhance_mode failed\n"); |
| 354 | return -1; |
| 355 | } |
| 356 | |
| 357 | exynos_dp_enable_enhanced_mode(enhance_mode); |
| 358 | |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info, |
| 363 | unsigned char *status) |
| 364 | { |
| 365 | unsigned int ret, i; |
| 366 | unsigned char buf[2]; |
| 367 | unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; |
| 368 | const unsigned char shift_val[] = {0, 4, 0, 4}; |
| 369 | |
| 370 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf); |
| 371 | if (ret != EXYNOS_DP_SUCCESS) { |
| 372 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 373 | return ret; |
| 374 | } |
| 375 | |
| 376 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 377 | lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; |
| 378 | if (lane_stat[0] != lane_stat[i]) { |
| 379 | printk(BIOS_ERR, "Wrong lane status\n"); |
| 380 | return -1; |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | *status = lane_stat[0]; |
| 385 | |
| 386 | return ret; |
| 387 | } |
| 388 | |
| 389 | static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num, |
| 390 | unsigned char *sw, unsigned char *em) |
| 391 | { |
| 392 | const unsigned char shift_val[] = {0, 4, 0, 4}; |
| 393 | unsigned int ret; |
| 394 | unsigned char buf; |
| 395 | unsigned int dpcd_addr; |
| 396 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 397 | /*lane_num value is used as array index, so this range 0 ~ 3 */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 398 | dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); |
| 399 | |
| 400 | ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); |
| 401 | if (ret != EXYNOS_DP_SUCCESS) { |
| 402 | printk(BIOS_ERR, "DP read adjust request failed\n"); |
| 403 | return -1; |
| 404 | } |
| 405 | |
| 406 | *sw = ((buf >> shift_val[lane_num]) & 0x03); |
| 407 | *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; |
| 408 | |
| 409 | return ret; |
| 410 | } |
| 411 | |
| 412 | static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info) |
| 413 | { |
| 414 | int ret; |
| 415 | |
| 416 | ret = exynos_dp_training_pattern_dis(); |
| 417 | if (ret != EXYNOS_DP_SUCCESS) { |
| 418 | printk(BIOS_ERR, "DP training_patter_disable() failed\n"); |
| 419 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 420 | } |
| 421 | |
| 422 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); |
| 423 | if (ret != EXYNOS_DP_SUCCESS) { |
| 424 | printk(BIOS_ERR, "DP set_enhanced_mode() failed\n"); |
| 425 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 426 | } |
| 427 | |
| 428 | return ret; |
| 429 | } |
| 430 | |
| 431 | static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info) |
| 432 | { |
| 433 | int ret; |
| 434 | |
| 435 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 436 | edp_info->lane_bw = DP_LANE_BW_1_62; |
| 437 | printk(BIOS_ERR, "DP Change lane bw to 1.62Gbps\n"); |
| 438 | edp_info->lt_info.lt_status = DP_LT_START; |
| 439 | ret = EXYNOS_DP_SUCCESS; |
| 440 | } else { |
| 441 | ret = exynos_dp_training_pattern_dis(); |
| 442 | if (ret != EXYNOS_DP_SUCCESS) |
| 443 | printk(BIOS_ERR, "DP training_patter_disable() failed\n"); |
| 444 | |
| 445 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); |
| 446 | if (ret != EXYNOS_DP_SUCCESS) |
| 447 | printk(BIOS_ERR, "DP set_enhanced_mode() failed\n"); |
| 448 | |
| 449 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 450 | } |
| 451 | |
| 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info |
| 456 | *edp_info) |
| 457 | { |
| 458 | unsigned int ret; |
| 459 | unsigned char lane_stat; |
| 460 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; |
| 461 | unsigned int i; |
| 462 | unsigned char adj_req_sw; |
| 463 | unsigned char adj_req_em; |
| 464 | unsigned char buf[5]; |
| 465 | |
| 466 | mdelay(1); |
| 467 | |
| 468 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); |
| 469 | if (ret != EXYNOS_DP_SUCCESS) { |
| 470 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 471 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 472 | return ret; |
| 473 | } |
| 474 | |
| 475 | if (lane_stat & DP_LANE_STAT_CR_DONE) { |
| 476 | printk(BIOS_DEBUG,"DP clock Recovery training succeed\n"); |
| 477 | exynos_dp_set_training_pattern(TRAINING_PTN2); |
| 478 | |
| 479 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 480 | ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw, |
| 481 | &adj_req_em); |
| 482 | if (ret != EXYNOS_DP_SUCCESS) { |
| 483 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 484 | return ret; |
| 485 | } |
| 486 | |
| 487 | lt_ctl_val[i] = 0; |
| 488 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 489 | |
| 490 | if ((adj_req_sw == VOLTAGE_LEVEL_3) |
| 491 | || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 492 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | |
| 493 | MAX_PRE_EMPHASIS_REACH_3; |
| 494 | } |
| 495 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); |
| 496 | } |
| 497 | |
| 498 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; |
| 499 | buf[1] = lt_ctl_val[0]; |
| 500 | buf[2] = lt_ctl_val[1]; |
| 501 | buf[3] = lt_ctl_val[2]; |
| 502 | buf[4] = lt_ctl_val[3]; |
| 503 | |
| 504 | ret = exynos_dp_write_bytes_to_dpcd( |
| 505 | DPCD_TRAINING_PATTERN_SET, 5, buf); |
| 506 | if (ret != EXYNOS_DP_SUCCESS) { |
| 507 | printk(BIOS_ERR, "DP write training pattern1 failed\n"); |
| 508 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 509 | return ret; |
| 510 | } else |
| 511 | edp_info->lt_info.lt_status = DP_LT_ET; |
| 512 | } else { |
| 513 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 514 | lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i); |
| 515 | ret = exynos_dp_read_dpcd_adj_req(i, |
| 516 | &adj_req_sw, &adj_req_em); |
| 517 | if (ret != EXYNOS_DP_SUCCESS) { |
| 518 | printk(BIOS_ERR, "DP read adj req failed\n"); |
| 519 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 524 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) |
| 525 | ret = exynos_dp_reduce_link_rate(edp_info); |
| 526 | |
| 527 | if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == |
| 528 | adj_req_sw) && |
| 529 | (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == |
| 530 | adj_req_em)) { |
| 531 | edp_info->lt_info.cr_loop[i]++; |
| 532 | if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP) |
| 533 | ret = exynos_dp_reduce_link_rate( |
| 534 | edp_info); |
| 535 | } |
| 536 | |
| 537 | lt_ctl_val[i] = 0; |
| 538 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 539 | |
| 540 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 541 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 542 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | |
| 543 | MAX_PRE_EMPHASIS_REACH_3; |
| 544 | } |
| 545 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); |
| 546 | } |
| 547 | |
| 548 | ret = exynos_dp_write_bytes_to_dpcd( |
| 549 | DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); |
| 550 | if (ret != EXYNOS_DP_SUCCESS) { |
| 551 | printk(BIOS_ERR, "DP write training pattern2 failed\n"); |
| 552 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 553 | return ret; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | return ret; |
| 558 | } |
| 559 | |
| 560 | static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info |
| 561 | *edp_info) |
| 562 | { |
| 563 | unsigned int ret; |
| 564 | unsigned char lane_stat, adj_req_sw, adj_req_em, i; |
| 565 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; |
| 566 | unsigned char interlane_aligned = 0; |
| 567 | unsigned char f_bw; |
| 568 | unsigned char f_lane_cnt; |
| 569 | unsigned char sink_stat; |
| 570 | |
| 571 | mdelay(1); |
| 572 | |
| 573 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); |
| 574 | if (ret != EXYNOS_DP_SUCCESS) { |
| 575 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 576 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 577 | return ret; |
| 578 | } |
| 579 | |
| 580 | printk(BIOS_DEBUG,"DP lane stat : %x\n", lane_stat); |
| 581 | |
| 582 | if (lane_stat & DP_LANE_STAT_CR_DONE) { |
| 583 | printk(BIOS_DEBUG, "DP_LANE_STAT_CR_DONE ok\n"); |
| 584 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED, |
| 585 | &sink_stat); |
| 586 | if (ret != EXYNOS_DP_SUCCESS) { |
| 587 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 588 | printk(BIOS_ERR, "DP read DPCD_LN_ALIGN_UPDATED failed\n"); |
| 589 | return ret; |
| 590 | } |
| 591 | |
| 592 | interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); |
| 593 | printk(BIOS_DEBUG, "interlane_aligned: %d\n", interlane_aligned); |
| 594 | printk(BIOS_DEBUG, "Check %d lanes\n", edp_info->lane_cnt); |
| 595 | |
| 596 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 597 | ret = exynos_dp_read_dpcd_adj_req(i, |
| 598 | &adj_req_sw, &adj_req_em); |
| 599 | if (ret != EXYNOS_DP_SUCCESS) { |
| 600 | printk(BIOS_ERR, "DP read adj req 1 failed\n"); |
| 601 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 602 | |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | lt_ctl_val[i] = 0; |
| 607 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 608 | |
| 609 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 610 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 611 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; |
| 612 | lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; |
| 613 | } |
| 614 | } |
| 615 | |
| 616 | if (((lane_stat&DP_LANE_STAT_CE_DONE) && |
| 617 | (lane_stat&DP_LANE_STAT_SYM_LOCK)) |
| 618 | && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { |
| 619 | printk(BIOS_DEBUG,"DP Equalizer training succeed\n"); |
| 620 | |
| 621 | f_bw = exynos_dp_get_link_bandwidth(); |
| 622 | f_lane_cnt = exynos_dp_get_lane_count(); |
| 623 | |
| 624 | printk(BIOS_DEBUG,"DP final BandWidth : %x\n", f_bw); |
| 625 | printk(BIOS_DEBUG,"DP final Lane Count : %x\n", f_lane_cnt); |
| 626 | |
| 627 | edp_info->lt_info.lt_status = DP_LT_FINISHED; |
| 628 | |
| 629 | exynos_dp_equalizer_err_link(edp_info); |
| 630 | |
| 631 | } else { |
| 632 | edp_info->lt_info.ep_loop++; |
| 633 | |
| 634 | if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) { |
| 635 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 636 | ret = exynos_dp_reduce_link_rate( |
| 637 | edp_info); |
| 638 | } else { |
| 639 | edp_info->lt_info.lt_status = |
| 640 | DP_LT_FAIL; |
| 641 | exynos_dp_equalizer_err_link(edp_info); |
| 642 | } |
| 643 | } else { |
| 644 | for (i = 0; i < edp_info->lane_cnt; i++) |
| 645 | exynos_dp_set_lanex_pre_emphasis( |
| 646 | lt_ctl_val[i], i); |
| 647 | |
| 648 | ret = exynos_dp_write_bytes_to_dpcd( |
| 649 | DPCD_TRAINING_LANE0_SET, |
| 650 | 4, lt_ctl_val); |
| 651 | if (ret != EXYNOS_DP_SUCCESS) { |
| 652 | printk(BIOS_ERR, "DP set lt pattern failed\n"); |
| 653 | edp_info->lt_info.lt_status = |
| 654 | DP_LT_FAIL; |
| 655 | exynos_dp_equalizer_err_link(edp_info); |
| 656 | } |
| 657 | } |
| 658 | } |
| 659 | } else if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 660 | ret = exynos_dp_reduce_link_rate(edp_info); |
| 661 | } else { |
| 662 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 663 | exynos_dp_equalizer_err_link(edp_info); |
| 664 | } |
| 665 | |
| 666 | return ret; |
| 667 | } |
| 668 | |
| 669 | static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info) |
| 670 | { |
| 671 | /* the C compiler is almost smart enough to know this gets set. |
| 672 | * But not quite. |
| 673 | */ |
| 674 | unsigned int ret = 0; |
| 675 | int training_finished; |
| 676 | |
| 677 | /* Turn off unnecessary lane */ |
| 678 | if (edp_info->lane_cnt == 1) |
| 679 | exynos_dp_set_analog_power_down(CH1_BLOCK, 1); |
| 680 | |
| 681 | training_finished = 0; |
| 682 | |
| 683 | edp_info->lt_info.lt_status = DP_LT_START; |
| 684 | |
| 685 | /* Process here */ |
| 686 | while (!training_finished) { |
| 687 | switch (edp_info->lt_info.lt_status) { |
| 688 | case DP_LT_START: |
| 689 | ret = exynos_dp_link_start(edp_info); |
| 690 | if (ret != EXYNOS_DP_SUCCESS) { |
| 691 | printk(BIOS_ERR, "DP LT:link start failed\n"); |
| 692 | training_finished = 1; |
| 693 | } |
| 694 | break; |
| 695 | case DP_LT_CR: |
| 696 | ret = exynos_dp_process_clock_recovery(edp_info); |
| 697 | if (ret != EXYNOS_DP_SUCCESS) { |
| 698 | printk(BIOS_ERR, "DP LT:clock recovery failed\n"); |
| 699 | training_finished = 1; |
| 700 | } |
| 701 | break; |
| 702 | case DP_LT_ET: |
| 703 | ret = exynos_dp_process_equalizer_training(edp_info); |
| 704 | if (ret != EXYNOS_DP_SUCCESS) { |
| 705 | printk(BIOS_ERR, "DP LT:equalizer training failed\n"); |
| 706 | training_finished = 1; |
| 707 | } |
| 708 | break; |
| 709 | case DP_LT_FINISHED: |
| 710 | training_finished = 1; |
| 711 | break; |
| 712 | case DP_LT_FAIL: |
| 713 | printk(BIOS_ERR,"DP: %s: DP_LT_FAIL: failed\n", __func__); |
| 714 | training_finished = 1; |
| 715 | ret = -1; |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | return ret; |
| 720 | } |
| 721 | |
| 722 | static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info) |
| 723 | { |
| 724 | unsigned int ret; |
| 725 | |
| 726 | exynos_dp_init_training(); |
| 727 | |
| 728 | ret = exynos_dp_sw_link_training(edp_info); |
| 729 | if (ret != EXYNOS_DP_SUCCESS) |
| 730 | printk(BIOS_ERR, "DP dp_sw_link_traning() failed\n"); |
| 731 | |
| 732 | return ret; |
| 733 | } |
| 734 | |
| 735 | static void exynos_dp_enable_scramble(unsigned int enable) |
| 736 | { |
| 737 | unsigned char data; |
| 738 | |
| 739 | if (enable) { |
| 740 | exynos_dp_enable_scrambling(DP_ENABLE); |
| 741 | |
| 742 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 743 | &data); |
| 744 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 745 | (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); |
| 746 | } else { |
| 747 | exynos_dp_enable_scrambling(DP_DISABLE); |
| 748 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 749 | &data); |
| 750 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 751 | (u8)(data | DPCD_SCRAMBLING_DISABLED)); |
| 752 | } |
| 753 | } |
| 754 | |
| 755 | static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) |
| 756 | { |
| 757 | unsigned int ret = 0; |
| 758 | unsigned int retry_cnt; |
| 759 | |
| 760 | mdelay(1); |
| 761 | |
| 762 | if (edp_info->video_info.master_mode) { |
| 763 | printk(BIOS_ERR, |
| 764 | "DP does not support master mode: bailing out\n"); |
| 765 | return -1; |
| 766 | } else { |
| 767 | /* debug slave */ |
| 768 | exynos_dp_config_video_slave_mode(&edp_info->video_info); |
| 769 | } |
| 770 | |
| 771 | exynos_dp_set_video_color_format(&edp_info->video_info); |
| 772 | |
| 773 | ret = exynos_dp_get_pll_lock_status(); |
| 774 | if (ret != PLL_LOCKED) { |
| 775 | printk(BIOS_ERR, "DP PLL is not locked yet\n"); |
| 776 | return -1; |
| 777 | } |
| 778 | |
| 779 | if (edp_info->video_info.master_mode == 0) { |
| 780 | retry_cnt = 10; |
| 781 | while (retry_cnt) { |
| 782 | ret = exynos_dp_is_slave_video_stream_clock_on(); |
| 783 | if (ret != EXYNOS_DP_SUCCESS) { |
| 784 | if (retry_cnt == 0) { |
| 785 | printk(BIOS_ERR, "DP stream_clock_on failed\n"); |
| 786 | return ret; |
| 787 | } |
| 788 | retry_cnt--; |
| 789 | mdelay(1); |
| 790 | } else { |
| 791 | printk(BIOS_DEBUG, "DP stream_clock succeeds\n"); |
| 792 | break; |
| 793 | } |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | /* Set to use the register calculated M/N video */ |
| 798 | exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0); |
| 799 | |
| 800 | /* For video bist, Video timing must be generated by register |
| 801 | * not clear if we still need this. We could take it out and it |
| 802 | * might appear to work, then fail strangely. |
| 803 | */ |
| 804 | exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE); |
| 805 | |
| 806 | /* we need to be sure this is off. */ |
| 807 | exynos_dp_disable_video_bist(); |
| 808 | |
| 809 | /* Disable video mute */ |
| 810 | exynos_dp_enable_video_mute(DP_DISABLE); |
| 811 | |
| 812 | /* Configure video Master or Slave mode */ |
| 813 | exynos_dp_enable_video_master(edp_info->video_info.master_mode); |
| 814 | |
| 815 | /* Enable video */ |
| 816 | exynos_dp_start_video(); |
| 817 | |
| 818 | if (edp_info->video_info.master_mode == 0) { |
Ronald G. Minnich | cff6667 | 2013-08-29 09:16:25 -0700 | [diff] [blame] | 819 | retry_cnt = 500; |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 820 | while (retry_cnt) { |
| 821 | ret = exynos_dp_is_video_stream_on(); |
| 822 | if (ret != EXYNOS_DP_SUCCESS) { |
| 823 | retry_cnt--; |
| 824 | if (retry_cnt == 0) { |
| 825 | printk(BIOS_ERR, "DP Timeout of video stream\n"); |
| 826 | } |
| 827 | } else { |
| 828 | printk(BIOS_DEBUG, "DP video stream is on\n"); |
| 829 | break; |
| 830 | } |
Ronald G. Minnich | cff6667 | 2013-08-29 09:16:25 -0700 | [diff] [blame] | 831 | /* this is a cheap operation, involving some register |
| 832 | * reads, and no AUX channel IO. A ms. delay is fine. |
| 833 | */ |
| 834 | mdelay(1); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 835 | } |
| 836 | } |
| 837 | |
| 838 | return ret; |
| 839 | } |
| 840 | |
| 841 | int exynos_init_dp(struct edp_device_info *edp_info) |
| 842 | { |
| 843 | unsigned int ret; |
| 844 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 845 | dp_phy_control(1); |
| 846 | |
| 847 | ret = exynos_dp_init_dp(); |
| 848 | if (ret != EXYNOS_DP_SUCCESS) { |
| 849 | printk(BIOS_ERR, "DP exynos_dp_init_dp() failed\n"); |
| 850 | return ret; |
| 851 | } |
| 852 | |
| 853 | ret = exynos_dp_handle_edid(edp_info); |
| 854 | if (ret != EXYNOS_DP_SUCCESS) { |
| 855 | printk(BIOS_ERR, "EDP handle_edid fail\n"); |
| 856 | return ret; |
| 857 | } |
| 858 | |
| 859 | ret = exynos_dp_set_link_train(edp_info); |
| 860 | if (ret != EXYNOS_DP_SUCCESS) { |
| 861 | printk(BIOS_ERR, "DP link training fail\n"); |
| 862 | return ret; |
| 863 | } |
| 864 | printk(BIOS_DEBUG, "EDP link training ok\n"); |
| 865 | |
| 866 | exynos_dp_enable_scramble(DP_ENABLE); |
| 867 | exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE); |
| 868 | exynos_dp_enable_enhanced_mode(DP_ENABLE); |
| 869 | |
| 870 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); |
| 871 | exynos_dp_set_lane_count(edp_info->lane_cnt); |
| 872 | |
| 873 | exynos_dp_init_video(); |
| 874 | ret = exynos_dp_config_video(edp_info); |
| 875 | |
| 876 | if (ret != EXYNOS_DP_SUCCESS) { |
| 877 | printk(BIOS_ERR, "Exynos DP init failed\n"); |
| 878 | return ret; |
| 879 | } |
| 880 | printk(BIOS_DEBUG, "Exynos DP init done\n"); |
| 881 | |
| 882 | return ret; |
| 883 | } |