Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Hung-Te Lin | 6fe0cab | 2013-01-22 18:57:56 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 5 | #include <boot_device.h> |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 6 | #include <console/console.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 7 | #include <soc/clk.h> |
| 8 | #include <soc/gpio.h> |
| 9 | #include <soc/spi.h> |
Elyes HAOUAS | 7884c22 | 2020-07-27 08:12:59 +0200 | [diff] [blame] | 10 | #include <stddef.h> |
| 11 | #include <stdint.h> |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 12 | #include <symbols.h> |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 13 | |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 14 | #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI |
| 15 | # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x) |
| 16 | #else |
| 17 | # define DEBUG_SPI(x,...) |
| 18 | #endif |
| 19 | |
| 20 | static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, |
| 21 | void *dinp, void const *doutp, int i) |
| 22 | { |
| 23 | int rx_lvl, tx_lvl; |
Stefan Reinauer | 1cf46a7 | 2013-02-14 17:06:43 -0800 | [diff] [blame] | 24 | unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); |
| 25 | unsigned int out_bytes, in_bytes; |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 26 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 27 | // TODO In current implementation, every read/write must be aligned to |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 28 | // 4 bytes, otherwise you may get timeout or other unexpected results. |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 29 | ASSERT(todo % 4 == 0); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 30 | |
| 31 | out_bytes = in_bytes = todo; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 32 | setbits32(®s->ch_cfg, SPI_CH_RST); |
| 33 | clrbits32(®s->ch_cfg, SPI_CH_RST); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 34 | write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 35 | |
| 36 | while (in_bytes) { |
| 37 | uint32_t spi_sts; |
| 38 | int temp; |
| 39 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 40 | spi_sts = read32(®s->spi_sts); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 41 | rx_lvl = ((spi_sts >> 15) & 0x7f); |
| 42 | tx_lvl = ((spi_sts >> 6) & 0x7f); |
| 43 | while (tx_lvl < 32 && out_bytes) { |
| 44 | // TODO The "writing" (tx) is not supported now; that's |
| 45 | // why we write garbage to keep driving FIFO clock. |
| 46 | temp = 0xffffffff; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 47 | write32(®s->tx_data, temp); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 48 | out_bytes -= 4; |
| 49 | tx_lvl += 4; |
| 50 | } |
| 51 | while (rx_lvl >= 4 && in_bytes) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 52 | temp = read32(®s->rx_data); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 53 | if (rxp) |
| 54 | *rxp++ = temp; |
| 55 | in_bytes -= 4; |
| 56 | rx_lvl -= 4; |
| 57 | } |
| 58 | } |
| 59 | } |
| 60 | |
David Hendricks | 0b153bd | 2013-02-09 17:24:17 -0800 | [diff] [blame] | 61 | /* set up SPI channel */ |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 62 | int exynos_spi_open(struct exynos_spi *regs) |
| 63 | { |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 64 | /* set the spi1 GPIO */ |
| 65 | |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 66 | /* set pktcnt and enable it */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 67 | write32(®s->pkt_cnt, 4 | SPI_PACKET_CNT_EN); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 68 | /* set FB_CLK_SEL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 69 | write32(®s->fb_clk, SPI_FB_DELAY_180); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 70 | /* set CH_WIDTH and BUS_WIDTH as word */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 71 | setbits32(®s->mode_cfg, |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 72 | SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 73 | clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 74 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 75 | /* clear rx and tx channel if set previously */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 76 | clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 77 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 78 | setbits32(®s->swap_cfg, |
| 79 | SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 80 | |
| 81 | /* do a soft reset */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 82 | setbits32(®s->ch_cfg, SPI_CH_RST); |
| 83 | clrbits32(®s->ch_cfg, SPI_CH_RST); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 84 | |
| 85 | /* now set rx and tx channel ON */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 86 | setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) |
| 91 | { |
| 92 | int upto, todo; |
| 93 | int i; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 94 | clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ |
Hung-Te Lin | e42030d | 2013-06-23 08:14:30 +0800 | [diff] [blame] | 95 | |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 96 | /* Send read instruction (0x3h) followed by a 24 bit addr */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 97 | write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 98 | |
| 99 | /* waiting for TX done */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 100 | while (!(read32(®s->spi_sts) & SPI_ST_TX_DONE)); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 101 | |
| 102 | for (upto = 0, i = 0; upto < len; upto += todo, i++) { |
| 103 | todo = MIN(len - upto, (1 << 15)); |
| 104 | exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); |
| 105 | } |
| 106 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 107 | setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 108 | |
Hung-Te Lin | e42030d | 2013-06-23 08:14:30 +0800 | [diff] [blame] | 109 | return len; |
| 110 | } |
| 111 | |
| 112 | int exynos_spi_close(struct exynos_spi *regs) |
| 113 | { |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 114 | /* |
| 115 | * Let put controller mode to BYTE as |
| 116 | * SPI driver does not support WORD mode yet |
| 117 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 118 | clrbits32(®s->mode_cfg, |
| 119 | SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 120 | write32(®s->swap_cfg, 0); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 121 | |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 122 | /* |
| 123 | * Flush spi tx, rx fifos and reset the SPI controller |
| 124 | * and clear rx/tx channel |
| 125 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 126 | clrsetbits32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); |
| 127 | clrbits32(®s->ch_cfg, SPI_CH_RST); |
| 128 | clrbits32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 129 | return 0; |
| 130 | } |
| 131 | |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 132 | static struct exynos_spi *boot_slave_regs; |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 133 | |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 134 | static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest, |
| 135 | size_t offset, size_t count) |
| 136 | { |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 137 | int bytes; |
| 138 | DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count); |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 139 | exynos_spi_open(boot_slave_regs); |
| 140 | bytes = exynos_spi_read(boot_slave_regs, dest, count, offset); |
| 141 | exynos_spi_close(boot_slave_regs); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 142 | return bytes; |
| 143 | } |
| 144 | |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 145 | static void *exynos_spi_map(const struct region_device *rdev, |
| 146 | size_t offset, size_t count) |
| 147 | { |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 148 | DEBUG_SPI("exynos_spi_cbfs_map\n"); |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 149 | // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and |
| 150 | // requires buffer memory address to be aligned. |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 151 | if (count % 4) |
| 152 | count += 4 - (count % 4); |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 153 | return mmap_helper_rdev_mmap(rdev, offset, count); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 154 | } |
| 155 | |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 156 | static const struct region_device_ops exynos_spi_ops = { |
| 157 | .mmap = exynos_spi_map, |
| 158 | .munmap = mmap_helper_rdev_munmap, |
| 159 | .readat = exynos_spi_readat, |
| 160 | }; |
| 161 | |
| 162 | static struct mmap_helper_region_device mdev = |
| 163 | MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE); |
| 164 | |
| 165 | void exynos_init_spi_boot_device(void) |
| 166 | { |
| 167 | boot_slave_regs = (void *)EXYNOS5_SPI1_BASE; |
| 168 | |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 169 | mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache)); |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 170 | } |
| 171 | |
Aaron Durbin | c6588c5 | 2015-05-15 13:15:34 -0500 | [diff] [blame] | 172 | const struct region_device *exynos_spi_boot_device(void) |
| 173 | { |
| 174 | return &mdev.rdev; |
Hung-Te Lin | 7e49405 | 2013-01-30 20:02:02 +0800 | [diff] [blame] | 175 | } |