| Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock |
| 9 | * must be placed after that. After the handoff, the space can be reclaimed. |
| 10 | */ |
| 11 | |
| 12 | SECTIONS |
| 13 | { |
| 14 | SRAM_START(0x2020000) |
| 15 | /* 13K hole, includes BL1 */ |
| 16 | BOOTBLOCK(0x2023400, 32K) |
| 17 | /* 19K hole */ |
| 18 | ROMSTAGE(0x2030000, 128K) |
| 19 | /* 32K hole */ |
| 20 | TTB(0x2058000, 16K) |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame^] | 21 | PRERAM_CBFS_CACHE(0x205C000, 68K) |
| 22 | CBFS_MCACHE(0x206D000, 8K) |
| Julius Werner | cefe89e | 2019-11-06 19:29:44 -0800 | [diff] [blame] | 23 | FMAP_CACHE(0x206F000, 2K) |
| Bill XIE | c79e96b | 2019-08-22 20:28:36 +0800 | [diff] [blame] | 24 | TPM_TCPA_LOG(0x206F800, 2K) |
| Joel Kitching | 0097f55 | 2019-02-21 12:36:55 +0800 | [diff] [blame] | 25 | VBOOT2_WORK(0x2070000, 12K) |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 26 | STACK(0x2074000, 16K) |
| 27 | SRAM_END(0x2078000) |
| 28 | |
| 29 | DRAM_START(0x40000000) |
| 30 | RAMSTAGE(0x40000000, 128K) |
| 31 | POSTRAM_CBFS_CACHE(0x41000000, 8M) |
| 32 | DMA_COHERENT(0x77300000, 1M) |
| 33 | } |