Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 2 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 3 | /* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */ |
| 4 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 6 | #include <console/console.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 7 | #include <delay.h> |
| 8 | #include <soc/clk.h> |
| 9 | #include <soc/cpu.h> |
| 10 | #include <soc/dmc.h> |
| 11 | #include <soc/setup.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 12 | |
| 13 | #define RDLVL_COMPLETE_TIMEOUT 10000 |
| 14 | |
| 15 | static void reset_phy_ctrl(void) |
| 16 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 17 | write32(&exynos_clock->lpddr3phy_ctrl, |
| 18 | LPDDR3PHY_CTRL_PHY_RESET_ENABLE); |
| 19 | write32(&exynos_clock->lpddr3phy_ctrl, |
| 20 | LPDDR3PHY_CTRL_PHY_RESET_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 21 | |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 22 | udelay(500); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 23 | } |
| 24 | |
Hung-Te Lin | 55c753d | 2013-04-25 16:14:19 +0800 | [diff] [blame] | 25 | int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, |
| 26 | int mem_reset) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 27 | { |
| 28 | unsigned int val; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 29 | int i; |
| 30 | |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 31 | if (mem_reset) |
Hung-Te Lin | 55c753d | 2013-04-25 16:14:19 +0800 | [diff] [blame] | 32 | reset_phy_ctrl(); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 33 | |
| 34 | /* Set Impedance Output Driver */ |
| 35 | val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | |
| 36 | (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | |
| 37 | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | |
| 38 | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 39 | write32(&exynos_phy0_control->phy_con39, val); |
| 40 | write32(&exynos_phy1_control->phy_con39, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 41 | |
| 42 | /* Set Read Latency and Burst Length for PHY0 and PHY1 */ |
| 43 | val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | |
| 44 | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 45 | write32(&exynos_phy0_control->phy_con42, val); |
| 46 | write32(&exynos_phy1_control->phy_con42, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 47 | |
| 48 | /* ZQ Calibration */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 49 | if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){ |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 50 | printk(BIOS_EMERG, "DRAM ZQ CALIBRATION FAILURE\n"); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 51 | return SETUP_ERR_ZQ_CALIBRATION_FAILURE; |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 52 | } |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 53 | |
| 54 | /* DQ Signal */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 55 | write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs); |
| 56 | write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 57 | |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 58 | write32(&exynos_dmc->concontrol, mem->concontrol | |
| 59 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 60 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 61 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 62 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 63 | |
| 64 | /* DQS Signal */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 65 | write32(&exynos_phy0_control->phy_con4, mem->phy0_dqs); |
| 66 | write32(&exynos_phy1_control->phy_con4, mem->phy1_dqs); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 67 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 68 | write32(&exynos_phy0_control->phy_con6, mem->phy0_dq); |
| 69 | write32(&exynos_phy1_control->phy_con6, mem->phy1_dq); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 70 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 71 | write32(&exynos_phy0_control->phy_con10, mem->phy0_tFS); |
| 72 | write32(&exynos_phy1_control->phy_con10, mem->phy1_tFS); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 73 | |
| 74 | val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 75 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 76 | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | |
| 77 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 78 | write32(&exynos_phy0_control->phy_con12, val); |
| 79 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 80 | |
| 81 | /* Start DLL locking */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 82 | write32(&exynos_phy0_control->phy_con12, |
| 83 | val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); |
| 84 | write32(&exynos_phy1_control->phy_con12, |
| 85 | val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 86 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 87 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 88 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 89 | write32(&exynos_dmc->concontrol, |
| 90 | mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 91 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 92 | /* Memory Channel Inteleaving Size */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 93 | write32(&exynos_dmc->ivcontrol, mem->iv_size); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 94 | |
| 95 | /* Set DMC MEMCONTROL register */ |
| 96 | val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 97 | write32(&exynos_dmc->memcontrol, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 98 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 99 | write32(&exynos_dmc->memconfig0, mem->memconfig); |
| 100 | write32(&exynos_dmc->memconfig1, mem->memconfig); |
| 101 | write32(&exynos_dmc->membaseconfig0, mem->membaseconfig0); |
| 102 | write32(&exynos_dmc->membaseconfig1, mem->membaseconfig1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 103 | |
| 104 | /* Precharge Configuration */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 105 | write32(&exynos_dmc->prechconfig, |
| 106 | mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 107 | |
| 108 | /* Power Down mode Configuration */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 109 | write32(&exynos_dmc->pwrdnconfig, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 110 | mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | |
| 111 | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 112 | |
| 113 | /* TimingRow, TimingData, TimingPower and Timingaref |
| 114 | * values as per Memory AC parameters |
| 115 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 116 | write32(&exynos_dmc->timingref, mem->timing_ref); |
| 117 | write32(&exynos_dmc->timingrow, mem->timing_row); |
| 118 | write32(&exynos_dmc->timingdata, mem->timing_data); |
| 119 | write32(&exynos_dmc->timingpower, mem->timing_power); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 120 | |
| 121 | /* Send PALL command */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 122 | dmc_config_prech(mem, exynos_dmc); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 123 | |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 124 | if (mem_reset) { |
| 125 | /* Send NOP, MRS and ZQINIT commands. |
| 126 | * Sending MRS command will reset the DRAM. We should not be |
| 127 | * reseting the DRAM after resume, this will lead to memory |
| 128 | * corruption as DRAM content is lost after DRAM reset |
| 129 | */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 130 | dmc_config_mrs(mem, exynos_dmc); |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 131 | } |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 132 | |
| 133 | if (mem->gate_leveling_enable) { |
| 134 | val = PHY_CON0_RESET_VAL; |
| 135 | val |= P0_CMD_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 136 | write32(&exynos_phy0_control->phy_con0, val); |
| 137 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 138 | |
| 139 | val = PHY_CON2_RESET_VAL; |
| 140 | val |= INIT_DESKEW_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 141 | write32(&exynos_phy0_control->phy_con2, val); |
| 142 | write32(&exynos_phy1_control->phy_con2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 143 | |
| 144 | val = PHY_CON0_RESET_VAL; |
| 145 | val |= P0_CMD_EN; |
| 146 | val |= BYTE_RDLVL_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 147 | write32(&exynos_phy0_control->phy_con0, val); |
| 148 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 149 | |
| 150 | val = (mem->ctrl_start_point << |
| 151 | PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 152 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 153 | (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | |
| 154 | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | |
| 155 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 156 | write32(&exynos_phy0_control->phy_con12, val); |
| 157 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 158 | |
| 159 | val = PHY_CON2_RESET_VAL; |
| 160 | val |= INIT_DESKEW_EN; |
| 161 | val |= RDLVL_GATE_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 162 | write32(&exynos_phy0_control->phy_con2, val); |
| 163 | write32(&exynos_phy1_control->phy_con2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 164 | |
| 165 | val = PHY_CON0_RESET_VAL; |
| 166 | val |= P0_CMD_EN; |
| 167 | val |= BYTE_RDLVL_EN; |
| 168 | val |= CTRL_SHGATE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 169 | write32(&exynos_phy0_control->phy_con0, val); |
| 170 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 171 | |
| 172 | val = PHY_CON1_RESET_VAL; |
| 173 | val &= ~(CTRL_GATEDURADJ_MASK); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 174 | write32(&exynos_phy0_control->phy_con1, val); |
| 175 | write32(&exynos_phy1_control->phy_con1, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 176 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 177 | write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 178 | i = RDLVL_COMPLETE_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 179 | while ((read32(&exynos_dmc->phystatus) & |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 180 | (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != |
| 181 | (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { |
| 182 | /* |
| 183 | * TODO(waihong): Comment on how long this take to |
| 184 | * timeout |
| 185 | */ |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 186 | udelay(1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 187 | i--; |
| 188 | } |
Ronald G. Minnich | 88e4691 | 2013-01-29 14:16:35 -0800 | [diff] [blame] | 189 | if (!i){ |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 190 | printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n"); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 191 | return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; |
Ronald G. Minnich | 88e4691 | 2013-01-29 14:16:35 -0800 | [diff] [blame] | 192 | } |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 193 | write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 194 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 195 | write32(&exynos_phy0_control->phy_con14, 0); |
| 196 | write32(&exynos_phy1_control->phy_con14, 0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 197 | |
| 198 | val = (mem->ctrl_start_point << |
| 199 | PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 200 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 201 | (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | |
| 202 | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | |
| 203 | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | |
| 204 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 205 | write32(&exynos_phy0_control->phy_con12, val); |
| 206 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 207 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 208 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /* Send PALL command */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 212 | dmc_config_prech(mem, exynos_dmc); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 213 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 214 | write32(&exynos_dmc->memcontrol, mem->memcontrol); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 215 | |
| 216 | /* Set DMC Concontrol and enable auto-refresh counter */ |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 217 | write32(&exynos_dmc->concontrol, mem->concontrol | |
| 218 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 219 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 220 | return 0; |
| 221 | } |