Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 6 | #include <reset.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 7 | #include <soc/addressmap.h> |
| 8 | #include <soc/clock.h> |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 9 | #include <soc/sdram.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 10 | #include <soc/grf.h> |
| 11 | #include <soc/soc.h> |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 12 | #include <timer.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 13 | #include <types.h> |
| 14 | |
| 15 | #define DDR_PI_OFFSET 0x800 |
| 16 | #define DDR_PHY_OFFSET 0x2000 |
| 17 | #define DDRC0_PI_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PI_OFFSET) |
| 18 | #define DDRC0_PHY_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PHY_OFFSET) |
| 19 | #define DDRC1_PI_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PI_OFFSET) |
| 20 | #define DDRC1_PHY_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PHY_OFFSET) |
| 21 | |
| 22 | static struct rk3399_ddr_pctl_regs * const rk3399_ddr_pctl[2] = { |
| 23 | (void *)DDRC0_BASE_ADDR, (void *)DDRC1_BASE_ADDR }; |
| 24 | static struct rk3399_ddr_pi_regs * const rk3399_ddr_pi[2] = { |
| 25 | (void *)DDRC0_PI_BASE_ADDR, (void *)DDRC1_PI_BASE_ADDR }; |
| 26 | static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = { |
| 27 | (void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR }; |
| 28 | static struct rk3399_msch_regs * const rk3399_msch[2] = { |
| 29 | (void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR }; |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 30 | static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * sys_reg bitfield struct |
| 34 | * [31] row_3_4_ch1 |
| 35 | * [30] row_3_4_ch0 |
| 36 | * [29:28] chinfo |
| 37 | * [27] rank_ch1 |
| 38 | * [26:25] col_ch1 |
| 39 | * [24] bk_ch1 |
| 40 | * [23:22] cs0_row_ch1 |
| 41 | * [21:20] cs1_row_ch1 |
| 42 | * [19:18] bw_ch1 |
| 43 | * [17:16] dbw_ch1; |
| 44 | * [15:13] ddrtype |
| 45 | * [12] channelnum |
| 46 | * [11] rank_ch0 |
| 47 | * [10:9] col_ch0 |
| 48 | * [8] bk_ch0 |
| 49 | * [7:6] cs0_row_ch0 |
| 50 | * [5:4] cs1_row_ch0 |
| 51 | * [3:2] bw_ch0 |
| 52 | * [1:0] dbw_ch0 |
| 53 | */ |
| 54 | #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) |
| 55 | #define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1) |
| 56 | #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) |
| 57 | #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) |
| 58 | #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) |
| 59 | #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1)) |
| 60 | #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) |
| 61 | #define SYS_REG_DEC_RANK(n, ch) (1 + ((n >> (11 + 16 * ch)) & 0x1)) |
| 62 | #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) |
| 63 | #define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) & 0x3)) |
| 64 | #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) \ |
| 65 | << (8 + ((ch) * 16))) |
| 66 | #define SYS_REG_DEC_BK(n, ch) (3 - ((n >> (8 + 16 * ch)) & 0x1)) |
| 67 | #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16))) |
| 68 | #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) & 0x3)) |
| 69 | #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16))) |
| 70 | #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) & 0x3)) |
| 71 | #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) |
| 72 | #define SYS_REG_DEC_BW(n, ch) (2 >> ((n >> (2 + 16 * ch)) & 0x3)) |
| 73 | #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) |
| 74 | #define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3)) |
| 75 | |
| 76 | #define DDR_STRIDE(n) write32(&rk3399_pmusgrf->soc_con4,\ |
| 77 | (0x1F << (10 + 16)) | (n << 10)) |
| 78 | |
| 79 | #define PRESET_SGRF_HOLD(n) ((0x1 << (6+16)) | ((n) << 6)) |
| 80 | #define PRESET_GPIO0_HOLD(n) ((0x1 << (7+16)) | ((n) << 7)) |
| 81 | #define PRESET_GPIO1_HOLD(n) ((0x1 << (8+16)) | ((n) << 8)) |
| 82 | |
| 83 | #define PHY_DRV_ODT_Hi_Z (0x0) |
| 84 | #define PHY_DRV_ODT_240 (0x1) |
| 85 | #define PHY_DRV_ODT_120 (0x8) |
| 86 | #define PHY_DRV_ODT_80 (0x9) |
| 87 | #define PHY_DRV_ODT_60 (0xc) |
| 88 | #define PHY_DRV_ODT_48 (0xd) |
| 89 | #define PHY_DRV_ODT_40 (0xe) |
| 90 | #define PHY_DRV_ODT_34_3 (0xf) |
| 91 | |
Derek Basehore | 5282fe6 | 2016-06-17 23:29:18 -0700 | [diff] [blame] | 92 | static void copy_to_reg(u32 *dest, const u32 *src, u32 n) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 93 | { |
| 94 | int i; |
| 95 | |
| 96 | for (i = 0; i < n / sizeof(u32); i++) { |
| 97 | write32(dest, *src); |
| 98 | src++; |
| 99 | dest++; |
| 100 | } |
| 101 | } |
| 102 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 103 | static void phy_dll_bypass_set(u32 channel, |
| 104 | struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) |
| 105 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 106 | u32 *denali_phy = ddr_publ_regs->denali_phy; |
| 107 | |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 108 | if (freq <= 125*MHz) { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 109 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 110 | setbits32(&denali_phy[86], (0x3 << 2) << 8); |
| 111 | setbits32(&denali_phy[214], (0x3 << 2) << 8); |
| 112 | setbits32(&denali_phy[342], (0x3 << 2) << 8); |
| 113 | setbits32(&denali_phy[470], (0x3 << 2) << 8); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 114 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 115 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 116 | setbits32(&denali_phy[547], (0x3 << 2) << 16); |
| 117 | setbits32(&denali_phy[675], (0x3 << 2) << 16); |
| 118 | setbits32(&denali_phy[803], (0x3 << 2) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 119 | } else { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 120 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 121 | clrbits32(&denali_phy[86], (0x3 << 2) << 8); |
| 122 | clrbits32(&denali_phy[214], (0x3 << 2) << 8); |
| 123 | clrbits32(&denali_phy[342], (0x3 << 2) << 8); |
| 124 | clrbits32(&denali_phy[470], (0x3 << 2) << 8); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 125 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 126 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 127 | clrbits32(&denali_phy[547], (0x3 << 2) << 16); |
| 128 | clrbits32(&denali_phy[675], (0x3 << 2) << 16); |
| 129 | clrbits32(&denali_phy[803], (0x3 << 2) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 130 | } |
| 131 | } |
| 132 | |
| 133 | static void set_memory_map(u32 channel, |
| 134 | const struct rk3399_sdram_params *sdram_params) |
| 135 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 136 | const struct rk3399_sdram_channel *sdram_ch = |
| 137 | &sdram_params->ch[channel]; |
| 138 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
| 139 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 140 | u32 cs_map; |
| 141 | u32 reduc; |
Lin Huang | 60687b5 | 2016-10-17 10:31:30 +0800 | [diff] [blame] | 142 | u32 row; |
| 143 | |
| 144 | if ((sdram_ch->ddrconfig < 2) || (sdram_ch->ddrconfig == 4)) |
| 145 | row = 16; |
| 146 | else if (sdram_ch->ddrconfig == 3) |
| 147 | row = 14; |
| 148 | else |
| 149 | row = 15; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 150 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 151 | cs_map = (sdram_ch->rank > 1) ? 3 : 1; |
| 152 | reduc = (sdram_ch->bw == 2) ? 0 : 1; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 153 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 154 | clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); |
| 155 | clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), |
| 156 | ((3 - sdram_ch->bk) << 16) | |
| 157 | ((16 - row) << 24)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 158 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 159 | clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16), |
| 160 | cs_map | (reduc << 16)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 161 | |
| 162 | /* PI_199 PI_COL_DIFF:RW:0:4 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 163 | clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 164 | |
| 165 | /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 166 | clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), |
| 167 | ((3 - sdram_ch->bk) << 16) | |
| 168 | ((16 - row) << 24)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 169 | /* PI_41 PI_CS_MAP:RW:24:4 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 170 | clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 171 | if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) |
| 172 | write32(&denali_pi[34], 0x2EC7FFFF); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static void set_ds_odt(u32 channel, |
| 176 | const struct rk3399_sdram_params *sdram_params) |
| 177 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 178 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 179 | |
| 180 | u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 181 | u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 182 | u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 183 | u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 184 | u32 reg_value; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 185 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 186 | if (sdram_params->dramtype == LPDDR4) { |
| 187 | tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; |
| 188 | tsel_wr_select_p = PHY_DRV_ODT_40; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 189 | ca_tsel_wr_select_p = PHY_DRV_ODT_40; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 190 | tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; |
| 191 | |
| 192 | tsel_rd_select_n = PHY_DRV_ODT_240; |
| 193 | tsel_wr_select_n = PHY_DRV_ODT_40; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 194 | ca_tsel_wr_select_n = PHY_DRV_ODT_40; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 195 | tsel_idle_select_n = PHY_DRV_ODT_240; |
| 196 | } else if (sdram_params->dramtype == LPDDR3) { |
| 197 | tsel_rd_select_p = PHY_DRV_ODT_240; |
| 198 | tsel_wr_select_p = PHY_DRV_ODT_34_3; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 199 | ca_tsel_wr_select_p = PHY_DRV_ODT_48; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 200 | tsel_idle_select_p = PHY_DRV_ODT_240; |
| 201 | |
| 202 | tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; |
| 203 | tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 204 | ca_tsel_wr_select_n = PHY_DRV_ODT_48; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 205 | tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; |
| 206 | } else { |
| 207 | tsel_rd_select_p = PHY_DRV_ODT_240; |
| 208 | tsel_wr_select_p = PHY_DRV_ODT_34_3; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 209 | ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 210 | tsel_idle_select_p = PHY_DRV_ODT_240; |
| 211 | |
| 212 | tsel_rd_select_n = PHY_DRV_ODT_240; |
| 213 | tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 214 | ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 215 | tsel_idle_select_n = PHY_DRV_ODT_240; |
| 216 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 217 | |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 218 | if (sdram_params->odt == 1) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 219 | tsel_rd_en = 1; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 220 | else |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 221 | tsel_rd_en = 0; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 222 | |
| 223 | tsel_wr_en = 0; |
| 224 | tsel_idle_en = 0; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 225 | |
| 226 | /* |
| 227 | * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 |
| 228 | * sets termination values for read/idle cycles and drive strength |
| 229 | * for write cycles for DQ/DM |
| 230 | */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 231 | reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 232 | (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | |
| 233 | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 234 | clrsetbits32(&denali_phy[6], 0xffffff, reg_value); |
| 235 | clrsetbits32(&denali_phy[134], 0xffffff, reg_value); |
| 236 | clrsetbits32(&denali_phy[262], 0xffffff, reg_value); |
| 237 | clrsetbits32(&denali_phy[390], 0xffffff, reg_value); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 238 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 239 | /* |
| 240 | * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 |
| 241 | * sets termination values for read/idle cycles and drive strength |
| 242 | * for write cycles for DQS |
| 243 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 244 | clrsetbits32(&denali_phy[7], 0xffffff, reg_value); |
| 245 | clrsetbits32(&denali_phy[135], 0xffffff, reg_value); |
| 246 | clrsetbits32(&denali_phy[263], 0xffffff, reg_value); |
| 247 | clrsetbits32(&denali_phy[391], 0xffffff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 248 | |
| 249 | /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 250 | reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 251 | clrsetbits32(&denali_phy[544], 0xff, reg_value); |
| 252 | clrsetbits32(&denali_phy[672], 0xff, reg_value); |
| 253 | clrsetbits32(&denali_phy[800], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 254 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 255 | /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 256 | clrsetbits32(&denali_phy[928], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 257 | |
| 258 | /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 259 | clrsetbits32(&denali_phy[937], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 260 | |
| 261 | /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 262 | clrsetbits32(&denali_phy[935], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 263 | |
| 264 | /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 265 | clrsetbits32(&denali_phy[939], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 266 | |
| 267 | /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 268 | clrsetbits32(&denali_phy[929], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 269 | |
| 270 | /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 271 | clrsetbits32(&denali_phy[924], 0xff, |
| 272 | tsel_wr_select_n | (tsel_wr_select_p << 4)); |
| 273 | clrsetbits32(&denali_phy[925], 0xff, |
| 274 | tsel_rd_select_n | (tsel_rd_select_p << 4)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 275 | |
| 276 | /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 277 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 278 | << 16; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 279 | clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value); |
| 280 | clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value); |
| 281 | clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value); |
| 282 | clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 283 | |
| 284 | /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 285 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 286 | << 24; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 287 | clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value); |
| 288 | clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value); |
| 289 | clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value); |
| 290 | clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 291 | |
| 292 | /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 293 | reg_value = tsel_wr_en << 8; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 294 | clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value); |
| 295 | clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value); |
| 296 | clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 297 | |
| 298 | /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 299 | reg_value = tsel_wr_en << 17; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 300 | clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 301 | /* |
| 302 | * pad_rst/cke/cs/clk_term tsel 1bits |
| 303 | * DENALI_PHY_938/936/940/934 offset_17 |
| 304 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 305 | clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value); |
| 306 | clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value); |
| 307 | clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value); |
| 308 | clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value); |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 309 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 310 | /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 311 | clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 312 | } |
| 313 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 314 | static void phy_io_config(u32 channel, |
| 315 | const struct rk3399_sdram_params *sdram_params) |
| 316 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 317 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 318 | u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 319 | u32 mode_sel = 0; |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 320 | u32 reg_value; |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 321 | u32 drv_value, odt_value; |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 322 | u32 speed; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 323 | |
| 324 | /* vref setting */ |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 325 | if (sdram_params->dramtype == LPDDR4) { |
| 326 | /* LPDDR4 */ |
| 327 | vref_mode_dq = 0x6; |
| 328 | vref_value_dq = 0x1f; |
| 329 | vref_mode_ac = 0x6; |
| 330 | vref_value_ac = 0x1f; |
| 331 | } else if (sdram_params->dramtype == LPDDR3) { |
| 332 | if (sdram_params->odt == 1) { |
| 333 | vref_mode_dq = 0x5; /* LPDDR3 ODT */ |
| 334 | drv_value = (read32(&denali_phy[6]) >> 12) & 0xf; |
| 335 | odt_value = (read32(&denali_phy[6]) >> 4) & 0xf; |
| 336 | if (drv_value == PHY_DRV_ODT_48) { |
| 337 | switch (odt_value) { |
| 338 | case PHY_DRV_ODT_240: |
| 339 | vref_value_dq = 0x16; |
| 340 | break; |
| 341 | case PHY_DRV_ODT_120: |
| 342 | vref_value_dq = 0x26; |
| 343 | break; |
| 344 | case PHY_DRV_ODT_60: |
| 345 | vref_value_dq = 0x36; |
| 346 | break; |
| 347 | default: |
| 348 | die("Halting: Invalid ODT value.\n"); |
| 349 | } |
| 350 | } else if (drv_value == PHY_DRV_ODT_40) { |
| 351 | switch (odt_value) { |
| 352 | case PHY_DRV_ODT_240: |
| 353 | vref_value_dq = 0x19; |
| 354 | break; |
| 355 | case PHY_DRV_ODT_120: |
| 356 | vref_value_dq = 0x23; |
| 357 | break; |
| 358 | case PHY_DRV_ODT_60: |
| 359 | vref_value_dq = 0x31; |
| 360 | break; |
| 361 | default: |
| 362 | die("Halting: Invalid ODT value.\n"); |
| 363 | } |
| 364 | } else if (drv_value == PHY_DRV_ODT_34_3) { |
| 365 | switch (odt_value) { |
| 366 | case PHY_DRV_ODT_240: |
| 367 | vref_value_dq = 0x17; |
| 368 | break; |
| 369 | case PHY_DRV_ODT_120: |
| 370 | vref_value_dq = 0x20; |
| 371 | break; |
| 372 | case PHY_DRV_ODT_60: |
| 373 | vref_value_dq = 0x2e; |
| 374 | break; |
| 375 | default: |
| 376 | die("Halting: Invalid ODT value.\n"); |
| 377 | } |
| 378 | } else { |
| 379 | die("Halting: Invalid DRV value.\n"); |
| 380 | } |
| 381 | } else { |
| 382 | vref_mode_dq = 0x2; /* LPDDR3 */ |
| 383 | vref_value_dq = 0x1f; |
| 384 | } |
| 385 | vref_mode_ac = 0x2; |
| 386 | vref_value_ac = 0x1f; |
| 387 | } else if (sdram_params->dramtype == DDR3) { |
| 388 | /* DDR3L */ |
| 389 | vref_mode_dq = 0x1; |
| 390 | vref_value_dq = 0x1f; |
| 391 | vref_mode_ac = 0x1; |
| 392 | vref_value_ac = 0x1f; |
| 393 | } |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 394 | else |
| 395 | die("Halting: Unknown DRAM type.\n"); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 396 | |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 397 | reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; |
| 398 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 399 | /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 400 | clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 401 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 402 | clrsetbits32(&denali_phy[914], 0xfff, reg_value); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 403 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 404 | clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 405 | /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 406 | clrsetbits32(&denali_phy[915], 0xfff, reg_value); |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 407 | |
| 408 | reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; |
| 409 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 410 | /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 411 | clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 412 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 413 | if (sdram_params->dramtype == LPDDR4) |
| 414 | mode_sel = 0x6; |
| 415 | else if (sdram_params->dramtype == LPDDR3) |
| 416 | mode_sel = 0x0; |
| 417 | else if (sdram_params->dramtype == DDR3) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 418 | mode_sel = 0x1; |
| 419 | |
| 420 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 421 | clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 422 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 423 | clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 424 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 425 | clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 426 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 427 | clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 428 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 429 | clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 430 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 431 | clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 432 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 433 | clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 434 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 435 | clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 436 | |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 437 | /* speed setting */ |
| 438 | if (sdram_params->ddr_freq < 400 * MHz) |
| 439 | speed = 0x0; |
| 440 | else if (sdram_params->ddr_freq < 800 * MHz) |
| 441 | speed = 0x1; |
| 442 | else if (sdram_params->ddr_freq < 1200 * MHz) |
| 443 | speed = 0x2; |
| 444 | else |
| 445 | speed = 0x3; |
| 446 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 447 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 448 | clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 449 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 450 | clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 451 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 452 | clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 453 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 454 | clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 455 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 456 | clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 457 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 458 | clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 459 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 460 | clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 461 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 462 | clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 463 | } |
| 464 | |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 465 | static int pctl_cfg(u32 channel, |
| 466 | const struct rk3399_sdram_params *sdram_params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 467 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 468 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
| 469 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 470 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Derek Basehore | 5282fe6 | 2016-06-17 23:29:18 -0700 | [diff] [blame] | 471 | const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; |
| 472 | const u32 *params_phy = sdram_params->phy_regs.denali_phy; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 473 | u32 tmp, tmp1, tmp2; |
| 474 | u32 pwrup_srefresh_exit; |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 475 | struct stopwatch sw; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 476 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 477 | /* |
| 478 | * work around controller bug: |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 479 | * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed |
| 480 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 481 | copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], |
| 482 | sizeof(struct rk3399_ddr_pctl_regs) - 4); |
| 483 | write32(&denali_ctl[0], params_ctl[0]); |
Derek Basehore | 5282fe6 | 2016-06-17 23:29:18 -0700 | [diff] [blame] | 484 | copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 485 | sizeof(struct rk3399_ddr_pi_regs)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 486 | /* rank count need to set for init */ |
| 487 | set_memory_map(channel, sdram_params); |
| 488 | |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 489 | write32(&denali_phy[910], sdram_params->phy_regs.denali_phy[910]); |
| 490 | write32(&denali_phy[911], sdram_params->phy_regs.denali_phy[911]); |
| 491 | write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); |
| 492 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 493 | pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 494 | clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 495 | |
| 496 | /* PHY_DLL_RST_EN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 497 | clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 498 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 499 | setbits32(&denali_pi[0], START); |
| 500 | setbits32(&denali_ctl[0], START); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 501 | |
| 502 | while (1) { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 503 | tmp = read32(&denali_phy[920]); |
| 504 | tmp1 = read32(&denali_phy[921]); |
| 505 | tmp2 = read32(&denali_phy[922]); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 506 | if ((((tmp >> 16) & 0x1) == 0x1) && |
| 507 | (((tmp1 >> 16) & 0x1) == 0x1) && |
| 508 | (((tmp1 >> 0) & 0x1) == 0x1) && |
| 509 | (((tmp2 >> 0) & 0x1) == 0x1)) |
| 510 | break; |
| 511 | } |
| 512 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 513 | copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); |
| 514 | copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); |
| 515 | copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); |
| 516 | copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); |
| 517 | copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); |
| 518 | copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); |
| 519 | copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); |
| 520 | copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 521 | set_ds_odt(channel, sdram_params); |
| 522 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 523 | /* |
| 524 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 |
| 525 | * dqs_tsel_wr_end[7:4] add Half cycle |
| 526 | */ |
| 527 | tmp = (read32(&denali_phy[84]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 528 | clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 529 | tmp = (read32(&denali_phy[212]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 530 | clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 531 | tmp = (read32(&denali_phy[340]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 532 | clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 533 | tmp = (read32(&denali_phy[468]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 534 | clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 535 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 536 | /* |
| 537 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 |
| 538 | * dq_tsel_wr_end[7:4] add Half cycle |
| 539 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 540 | tmp = (read32(&denali_phy[83]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 541 | clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 542 | tmp = (read32(&denali_phy[211]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 543 | clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 544 | tmp = (read32(&denali_phy[339]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 545 | clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 546 | tmp = (read32(&denali_phy[467]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 547 | clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 548 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 549 | phy_io_config(channel, sdram_params); |
| 550 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 551 | /* PHY_DLL_RST_EN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 552 | clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 553 | |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 554 | /* FIXME: need to care ERROR bit */ |
| 555 | stopwatch_init_msecs_expire(&sw, 100); |
| 556 | while (!(read32(&denali_ctl[203]) & (1 << 3))) { |
| 557 | if (stopwatch_expired(&sw)) |
| 558 | return -1; |
| 559 | } |
| 560 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 561 | clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, |
| 562 | pwrup_srefresh_exit); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 563 | return 0; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 564 | } |
| 565 | |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 566 | static void select_per_cs_training_index(u32 channel, u32 rank) |
| 567 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 568 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 569 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 570 | /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 571 | if ((read32(&denali_phy[84])>>16) & 1) { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 572 | /* |
| 573 | * PHY_8/136/264/392 |
| 574 | * phy_per_cs_training_index_X 1bit offset_24 |
| 575 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 576 | clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24); |
| 577 | clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24); |
| 578 | clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24); |
| 579 | clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 580 | } |
| 581 | } |
| 582 | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 583 | static void override_write_leveling_value(u32 channel) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 584 | { |
Jianqun Xu | 681b6b9 | 2016-09-11 18:26:42 +0800 | [diff] [blame] | 585 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 586 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 587 | u32 byte; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 588 | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 589 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 590 | setbits32(&denali_phy[896], 1); |
Jianqun Xu | 681b6b9 | 2016-09-11 18:26:42 +0800 | [diff] [blame] | 591 | |
| 592 | /* |
| 593 | * PHY_8/136/264/392 |
| 594 | * phy_per_cs_training_multicast_en_X 1bit offset_16 |
| 595 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 596 | clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16); |
| 597 | clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16); |
| 598 | clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16); |
| 599 | clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16); |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 600 | |
| 601 | for (byte = 0; byte < 4; byte++) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 602 | clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16, |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 603 | 0x200 << 16); |
| 604 | |
| 605 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 606 | clrbits32(&denali_phy[896], 1); |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 607 | |
| 608 | /* CTL_200 ctrlupd_req 1bit offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 609 | clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 610 | } |
| 611 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 612 | static int data_training(u32 channel, |
| 613 | const struct rk3399_sdram_params *sdram_params, |
| 614 | u32 training_flag) |
| 615 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 616 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 617 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 618 | u32 i, tmp; |
| 619 | u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; |
| 620 | u32 rank = sdram_params->ch[channel].rank; |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 621 | u32 reg_value = 0; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 622 | |
| 623 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 624 | setbits32(&denali_phy[927], (1 << 22)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 625 | |
Patrick Georgi | e640716 | 2016-11-02 11:36:07 +0100 | [diff] [blame] | 626 | if (training_flag == PI_FULL_TRAINING) { |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 627 | if (sdram_params->dramtype == LPDDR4) { |
| 628 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
| 629 | PI_READ_GATE_TRAINING | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 630 | PI_READ_LEVELING | PI_WDQ_LEVELING; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 631 | } else if (sdram_params->dramtype == LPDDR3) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 632 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 633 | PI_READ_GATE_TRAINING; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 634 | } else if (sdram_params->dramtype == DDR3) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 635 | training_flag = PI_WRITE_LEVELING | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 636 | PI_READ_GATE_TRAINING | |
| 637 | PI_READ_LEVELING; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 638 | } |
| 639 | } |
| 640 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 641 | /* ca training(LPDDR4,LPDDR3 support) */ |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 642 | if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { |
| 643 | for (i = 0; i < rank; i++) { |
Derek Basehore | ba0b9ab | 2016-09-21 15:43:36 -0700 | [diff] [blame] | 644 | select_per_cs_training_index(channel, i); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 645 | /* PI_100 PI_CALVL_EN:RW:8:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 646 | clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 647 | /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 648 | clrsetbits32(&denali_pi[92], |
| 649 | (0x1 << 16) | (0x3 << 24), |
| 650 | (0x1 << 16) | (i << 24)); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 651 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 652 | while (1) { |
| 653 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 654 | tmp = read32(&denali_pi[174]) >> 8; |
| 655 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 656 | /* |
| 657 | * check status obs |
| 658 | * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 |
| 659 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 660 | obs_0 = read32(&denali_phy[532]); |
| 661 | obs_1 = read32(&denali_phy[660]); |
Lin Huang | 271a2c2 | 2016-07-26 10:29:45 +0800 | [diff] [blame] | 662 | obs_2 = read32(&denali_phy[788]); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 663 | if (((obs_0 >> 30) & 0x3) || |
| 664 | ((obs_1 >> 30) & 0x3) || |
| 665 | ((obs_2 >> 30) & 0x3)) |
| 666 | obs_err = 1; |
| 667 | if ((((tmp >> 11) & 0x1) == 0x1) && |
| 668 | (((tmp >> 13) & 0x1) == 0x1) && |
| 669 | (((tmp >> 5) & 0x1) == 0x0) && |
| 670 | (obs_err == 0)) |
| 671 | break; |
| 672 | else if ((((tmp >> 5) & 0x1) == 0x1) || |
| 673 | (obs_err == 1)) |
| 674 | return -1; |
| 675 | } |
| 676 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 677 | write32((&denali_pi[175]), 0x00003f7c); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 678 | } |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 679 | clrbits32(&denali_pi[100], 0x3 << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ |
| 683 | if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { |
| 684 | for (i = 0; i < rank; i++) { |
Derek Basehore | ba0b9ab | 2016-09-21 15:43:36 -0700 | [diff] [blame] | 685 | select_per_cs_training_index(channel, i); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 686 | /* PI_60 PI_WRLVL_EN:RW:8:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 687 | clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 688 | /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 689 | clrsetbits32(&denali_pi[59], |
| 690 | (0x1 << 8) | (0x3 << 16), |
| 691 | (0x1 << 8) | (i << 16)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 692 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 693 | while (1) { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 694 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 695 | tmp = read32(&denali_pi[174]) >> 8; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 696 | |
| 697 | /* |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 698 | * check status obs, if error maybe can not |
| 699 | * get leveling done PHY_40/168/296/424 |
| 700 | * phy_wrlvl_status_obs_X:0:13 |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 701 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 702 | obs_0 = read32(&denali_phy[40]); |
| 703 | obs_1 = read32(&denali_phy[168]); |
| 704 | obs_2 = read32(&denali_phy[296]); |
| 705 | obs_3 = read32(&denali_phy[424]); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 706 | if (((obs_0 >> 12) & 0x1) || |
| 707 | ((obs_1 >> 12) & 0x1) || |
| 708 | ((obs_2 >> 12) & 0x1) || |
| 709 | ((obs_3 >> 12) & 0x1)) |
| 710 | obs_err = 1; |
| 711 | if ((((tmp >> 10) & 0x1) == 0x1) && |
| 712 | (((tmp >> 13) & 0x1) == 0x1) && |
| 713 | (((tmp >> 4) & 0x1) == 0x0) && |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 714 | (obs_err == 0)) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 715 | break; |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 716 | else if ((((tmp >> 4) & 0x1) == 0x1) || |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 717 | (obs_err == 1)) |
| 718 | return -1; |
| 719 | } |
| 720 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 721 | write32((&denali_pi[175]), 0x00003f7c); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 722 | } |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 723 | |
| 724 | override_write_leveling_value(channel); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 725 | clrbits32(&denali_pi[60], 0x3 << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 726 | } |
| 727 | |
| 728 | /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ |
| 729 | if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 730 | |
| 731 | /* |
| 732 | * The differential signal of DQS needs to keep low level |
| 733 | * before gate training. RPULL will connect 4Kn from PADP |
| 734 | * to VSS and a 4Kn from PADN to VDDQ to ensure it. |
| 735 | * But if it has PHY side ODT connect at this time, |
| 736 | * it will change the DQS signal level. So disable PHY |
| 737 | * side ODT before gate training and restore ODT state |
| 738 | * after gate training. |
| 739 | */ |
| 740 | if (sdram_params->dramtype != LPDDR4) { |
| 741 | reg_value = (read32(&denali_phy[6]) >> 24) & 0x7; |
| 742 | |
| 743 | /* |
| 744 | * phy_dqs_tsel_enable_X 3bits |
| 745 | * DENALI_PHY_6/134/262/390 offset_24 |
| 746 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 747 | clrbits32(&denali_phy[6], 0x7 << 24); |
| 748 | clrbits32(&denali_phy[134], 0x7 << 24); |
| 749 | clrbits32(&denali_phy[262], 0x7 << 24); |
| 750 | clrbits32(&denali_phy[390], 0x7 << 24); |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 751 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 752 | for (i = 0; i < rank; i++) { |
Derek Basehore | ba0b9ab | 2016-09-21 15:43:36 -0700 | [diff] [blame] | 753 | select_per_cs_training_index(channel, i); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 754 | /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 755 | clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24); |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 756 | /* |
| 757 | * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 |
| 758 | * PI_RDLVL_CS:RW:24:2 |
| 759 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 760 | clrsetbits32(&denali_pi[74], |
| 761 | (0x1 << 16) | (0x3 << 24), |
| 762 | (0x1 << 16) | (i << 24)); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 763 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 764 | while (1) { |
| 765 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 766 | tmp = read32(&denali_pi[174]) >> 8; |
| 767 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 768 | /* |
| 769 | * check status obs |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 770 | * PHY_43/171/299/427 |
| 771 | * PHY_GTLVL_STATUS_OBS_x:16:8 |
| 772 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 773 | obs_0 = read32(&denali_phy[43]); |
| 774 | obs_1 = read32(&denali_phy[171]); |
| 775 | obs_2 = read32(&denali_phy[299]); |
| 776 | obs_3 = read32(&denali_phy[427]); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 777 | if (((obs_0 >> (16 + 6)) & 0x3) || |
| 778 | ((obs_1 >> (16 + 6)) & 0x3) || |
| 779 | ((obs_2 >> (16 + 6)) & 0x3) || |
| 780 | ((obs_3 >> (16 + 6)) & 0x3)) |
| 781 | obs_err = 1; |
| 782 | if ((((tmp >> 9) & 0x1) == 0x1) && |
| 783 | (((tmp >> 13) & 0x1) == 0x1) && |
| 784 | (((tmp >> 3) & 0x1) == 0x0) && |
| 785 | (obs_err == 0)) |
| 786 | break; |
| 787 | else if ((((tmp >> 3) & 0x1) == 0x1) || |
| 788 | (obs_err == 1)) |
| 789 | return -1; |
| 790 | } |
| 791 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 792 | write32((&denali_pi[175]), 0x00003f7c); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 793 | } |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 794 | clrbits32(&denali_pi[80], 0x3 << 24); |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 795 | |
| 796 | if (sdram_params->dramtype != LPDDR4) { |
| 797 | /* |
| 798 | * phy_dqs_tsel_enable_X 3bits |
| 799 | * DENALI_PHY_6/134/262/390 offset_24 |
| 800 | */ |
| 801 | tmp = reg_value << 24; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 802 | clrsetbits32(&denali_phy[6], 0x7 << 24, tmp); |
| 803 | clrsetbits32(&denali_phy[134], 0x7 << 24, tmp); |
| 804 | clrsetbits32(&denali_phy[262], 0x7 << 24, tmp); |
| 805 | clrsetbits32(&denali_phy[390], 0x7 << 24, tmp); |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 806 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |
| 810 | if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { |
| 811 | for (i = 0; i < rank; i++) { |
Derek Basehore | ba0b9ab | 2016-09-21 15:43:36 -0700 | [diff] [blame] | 812 | select_per_cs_training_index(channel, i); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 813 | /* PI_80 PI_RDLVL_EN:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 814 | clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 815 | /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 816 | clrsetbits32(&denali_pi[74], |
| 817 | (0x1 << 8) | (0x3 << 24), |
| 818 | (0x1 << 8) | (i << 24)); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 819 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 820 | while (1) { |
| 821 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 822 | tmp = read32(&denali_pi[174]) >> 8; |
| 823 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 824 | /* |
| 825 | * make sure status obs not report error bit |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 826 | * PHY_46/174/302/430 |
| 827 | * phy_rdlvl_status_obs_X:16:8 |
| 828 | */ |
| 829 | if ((((tmp >> 8) & 0x1) == 0x1) && |
| 830 | (((tmp >> 13) & 0x1) == 0x1) && |
| 831 | (((tmp >> 2) & 0x1) == 0x0)) |
| 832 | break; |
| 833 | else if (((tmp >> 2) & 0x1) == 0x1) |
| 834 | return -1; |
| 835 | } |
| 836 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 837 | write32((&denali_pi[175]), 0x00003f7c); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 838 | } |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 839 | clrbits32(&denali_pi[80], 0x3 << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | /* wdq leveling(LPDDR4 support) */ |
| 843 | if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { |
| 844 | for (i = 0; i < rank; i++) { |
Derek Basehore | ba0b9ab | 2016-09-21 15:43:36 -0700 | [diff] [blame] | 845 | select_per_cs_training_index(channel, i); |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 846 | /* |
| 847 | * disable PI_WDQLVL_VREF_EN before wdq leveling? |
| 848 | * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 |
| 849 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 850 | clrbits32(&denali_pi[181], 0x1 << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 851 | /* PI_124 PI_WDQLVL_EN:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 852 | clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 853 | /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 854 | clrsetbits32(&denali_pi[121], |
| 855 | (0x1 << 8) | (0x3 << 16), |
| 856 | (0x1 << 8) | (i << 16)); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 857 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 858 | while (1) { |
| 859 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 860 | tmp = read32(&denali_pi[174]) >> 8; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 861 | if ((((tmp >> 12) & 0x1) == 0x1) && |
| 862 | (((tmp >> 13) & 0x1) == 0x1) && |
| 863 | (((tmp >> 6) & 0x1) == 0x0)) |
| 864 | break; |
| 865 | else if (((tmp >> 6) & 0x1) == 0x1) |
| 866 | return -1; |
| 867 | } |
| 868 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 869 | write32((&denali_pi[175]), 0x00003f7c); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 870 | } |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 871 | clrbits32(&denali_pi[124], 0x3 << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 872 | } |
| 873 | |
| 874 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 875 | clrbits32(&denali_phy[927], (1 << 22)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 876 | |
| 877 | return 0; |
| 878 | } |
| 879 | |
| 880 | static void set_ddrconfig(const struct rk3399_sdram_params *sdram_params, |
| 881 | unsigned char channel, u32 ddrconfig) |
| 882 | { |
| 883 | /* only need to set ddrconfig */ |
| 884 | struct rk3399_msch_regs *ddr_msch_regs = rk3399_msch[channel]; |
| 885 | unsigned int cs0_cap = 0; |
| 886 | unsigned int cs1_cap = 0; |
| 887 | |
| 888 | cs0_cap = (1 << (sdram_params->ch[channel].cs0_row |
| 889 | + sdram_params->ch[channel].col |
| 890 | + sdram_params->ch[channel].bk |
| 891 | + sdram_params->ch[channel].bw - 20)); |
| 892 | if (sdram_params->ch[channel].rank > 1) |
| 893 | cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row |
| 894 | - sdram_params->ch[channel].cs1_row); |
| 895 | if (sdram_params->ch[channel].row_3_4) { |
| 896 | cs0_cap = cs0_cap * 3 / 4; |
| 897 | cs1_cap = cs1_cap * 3 / 4; |
| 898 | } |
| 899 | |
Lin Huang | 60687b5 | 2016-10-17 10:31:30 +0800 | [diff] [blame] | 900 | write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 8)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 901 | write32(&ddr_msch_regs->ddrsize, ((cs0_cap / 32) & 0xff) | |
| 902 | (((cs1_cap / 32) & 0xff) << 8)); |
| 903 | } |
| 904 | |
| 905 | static void dram_all_config(const struct rk3399_sdram_params *sdram_params) |
| 906 | { |
| 907 | u32 sys_reg = 0; |
| 908 | unsigned int channel; |
| 909 | unsigned int use; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 910 | |
| 911 | sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype); |
| 912 | sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->num_channels); |
| 913 | for (channel = 0, use = 0; |
| 914 | (use < sdram_params->num_channels) && (channel < 2); channel++) { |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 915 | const struct rk3399_sdram_channel *info = |
| 916 | &sdram_params->ch[channel]; |
Derek Basehore | 1dd0bc0 | 2016-06-23 14:35:22 -0700 | [diff] [blame] | 917 | struct rk3399_msch_regs *ddr_msch_regs; |
| 918 | const struct rk3399_msch_timings *noc_timing; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 919 | |
| 920 | if (sdram_params->ch[channel].col == 0) |
| 921 | continue; |
| 922 | use++; |
| 923 | sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); |
| 924 | sys_reg |= SYS_REG_ENC_CHINFO(channel); |
| 925 | sys_reg |= SYS_REG_ENC_RANK(info->rank, channel); |
| 926 | sys_reg |= SYS_REG_ENC_COL(info->col, channel); |
| 927 | sys_reg |= SYS_REG_ENC_BK(info->bk, channel); |
| 928 | sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 929 | if (sdram_params->ch[channel].rank > 1) |
| 930 | sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 931 | sys_reg |= SYS_REG_ENC_BW(info->bw, channel); |
| 932 | sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel); |
| 933 | |
Derek Basehore | 1dd0bc0 | 2016-06-23 14:35:22 -0700 | [diff] [blame] | 934 | ddr_msch_regs = rk3399_msch[channel]; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 935 | noc_timing = &sdram_params->ch[channel].noc_timings; |
| 936 | write32(&ddr_msch_regs->ddrtiminga0.d32, |
| 937 | noc_timing->ddrtiminga0.d32); |
| 938 | write32(&ddr_msch_regs->ddrtimingb0.d32, |
| 939 | noc_timing->ddrtimingb0.d32); |
| 940 | write32(&ddr_msch_regs->ddrtimingc0.d32, |
| 941 | noc_timing->ddrtimingc0.d32); |
| 942 | write32(&ddr_msch_regs->devtodev0.d32, |
| 943 | noc_timing->devtodev0.d32); |
| 944 | write32(&ddr_msch_regs->ddrmode.d32, |
| 945 | noc_timing->ddrmode.d32); |
| 946 | |
| 947 | /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ |
| 948 | if (sdram_params->ch[channel].rank == 1) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 949 | setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276], |
| 950 | 1 << 17); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 951 | } |
| 952 | |
| 953 | write32(&rk3399_pmugrf->os_reg2, sys_reg); |
| 954 | DDR_STRIDE(sdram_params->stride); |
| 955 | |
| 956 | /* reboot hold register set */ |
| 957 | write32(&pmucru_ptr->pmucru_rstnhold_con[1], |
| 958 | PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | |
| 959 | PRESET_GPIO1_HOLD(1)); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 960 | clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 961 | } |
| 962 | |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 963 | static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) |
| 964 | { |
| 965 | u32 channel; |
| 966 | u32 *denali_phy; |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 967 | struct stopwatch sw; |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 968 | u32 ch_count = sdram_params->num_channels; |
| 969 | |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 970 | stopwatch_init_msecs_expire(&sw, 100); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 971 | write32(&rk3399_ddr_cic->cic_ctrl0, |
| 972 | RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, |
| 973 | 1 << 4 | 1 << 2 | 1)); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 974 | while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) { |
| 975 | if (stopwatch_expired(&sw)) { |
| 976 | printk(BIOS_ERR, |
| 977 | "index1 frequency change overtime, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 978 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 979 | } |
| 980 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 981 | |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 982 | stopwatch_init_msecs_expire(&sw, 100); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 983 | write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 984 | while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) { |
| 985 | if (stopwatch_expired(&sw)) { |
| 986 | printk(BIOS_ERR, |
| 987 | "index1 frequency done overtime, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 988 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 989 | } |
| 990 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 991 | |
| 992 | for (channel = 0; channel < ch_count; channel++) { |
| 993 | denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 994 | clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); |
Patrick Georgi | e640716 | 2016-11-02 11:36:07 +0100 | [diff] [blame] | 995 | if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 996 | printk(BIOS_ERR, "index1 training failed, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 997 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 998 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 999 | } |
| 1000 | } |
| 1001 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1002 | void sdram_init(const struct rk3399_sdram_params *sdram_params) |
| 1003 | { |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1004 | unsigned char dramtype = sdram_params->dramtype; |
| 1005 | unsigned int ddr_freq = sdram_params->ddr_freq; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1006 | int channel; |
| 1007 | |
| 1008 | printk(BIOS_INFO, "Starting SDRAM initialization...\n"); |
| 1009 | |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1010 | if ((dramtype == DDR3 && ddr_freq > 800*MHz) || |
Lin Huang | ba2b63a | 2016-07-25 10:06:09 +0800 | [diff] [blame] | 1011 | (dramtype == LPDDR3 && ddr_freq > 933*MHz) || |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1012 | (dramtype == LPDDR4 && ddr_freq > 800*MHz)) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1013 | die("SDRAM frequency is to high!"); |
| 1014 | |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1015 | rkclk_configure_ddr(ddr_freq); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1016 | |
| 1017 | for (channel = 0; channel < 2; channel++) { |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1018 | phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1019 | |
| 1020 | if (channel >= sdram_params->num_channels) |
| 1021 | continue; |
| 1022 | |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1023 | /* |
| 1024 | * TODO: we need to find the root cause why this |
| 1025 | * step may fail, before that, we just reset the |
| 1026 | * system, and start again. |
| 1027 | */ |
| 1028 | if (pctl_cfg(channel, sdram_params) != 0) { |
| 1029 | printk(BIOS_ERR, "pctl_cfg fail, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1030 | board_reset(); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1031 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1032 | |
| 1033 | /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1034 | if (dramtype == LPDDR3) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1035 | udelay(10); |
| 1036 | |
Patrick Georgi | e640716 | 2016-11-02 11:36:07 +0100 | [diff] [blame] | 1037 | if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1038 | printk(BIOS_ERR, |
| 1039 | "SDRAM initialization failed, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1040 | board_reset(); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1041 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1042 | |
| 1043 | set_ddrconfig(sdram_params, channel, |
| 1044 | sdram_params->ch[channel].ddrconfig); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1045 | } |
| 1046 | dram_all_config(sdram_params); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1047 | switch_to_phy_index1(sdram_params); |
| 1048 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1049 | printk(BIOS_INFO, "Finish SDRAM initialization...\n"); |
| 1050 | } |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 1051 | |
| 1052 | size_t sdram_size_mb(void) |
| 1053 | { |
Lin Huang | f00af58 | 2016-11-15 11:40:58 +0800 | [diff] [blame] | 1054 | u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; |
| 1055 | size_t chipsize_mb = 0; |
| 1056 | static size_t size_mb = 0; |
| 1057 | u32 ch; |
| 1058 | |
| 1059 | if (!size_mb) { |
| 1060 | u32 sys_reg = read32(&rk3399_pmugrf->os_reg2); |
| 1061 | u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); |
| 1062 | |
| 1063 | for (ch = 0; ch < ch_num; ch++) { |
| 1064 | rank = SYS_REG_DEC_RANK(sys_reg, ch); |
| 1065 | col = SYS_REG_DEC_COL(sys_reg, ch); |
| 1066 | bk = SYS_REG_DEC_BK(sys_reg, ch); |
| 1067 | cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch); |
| 1068 | cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch); |
| 1069 | bw = SYS_REG_DEC_BW(sys_reg, ch); |
| 1070 | row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch); |
| 1071 | |
| 1072 | chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); |
| 1073 | |
| 1074 | if (rank > 1) |
| 1075 | chipsize_mb += chipsize_mb >> |
| 1076 | (cs0_row - cs1_row); |
| 1077 | if (row_3_4) |
| 1078 | chipsize_mb = chipsize_mb * 3 / 4; |
| 1079 | size_mb += chipsize_mb; |
| 1080 | } |
| 1081 | |
| 1082 | /* |
| 1083 | * we use the 0x00000000~0xf7ffffff space |
| 1084 | * since 0xf8000000~0xffffffff is soc register space |
| 1085 | * so we reserve it |
| 1086 | */ |
| 1087 | size_mb = MIN(size_mb, 0xf8000000/MiB); |
| 1088 | } |
| 1089 | |
| 1090 | return size_mb; |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 1091 | } |