Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Akash Asthana | 634c783 | 2019-07-29 18:11:15 +0530 | [diff] [blame] | 2 | |
| 3 | #include <spi-generic.h> |
| 4 | #include <spi_flash.h> |
| 5 | #include <arch/cache.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <soc/addressmap.h> |
| 8 | #include <soc/qspi.h> |
| 9 | #include <soc/gpio.h> |
| 10 | #include <soc/clock.h> |
| 11 | #include <symbols.h> |
| 12 | #include <assert.h> |
| 13 | #include <gpio.h> |
| 14 | #include <string.h> |
| 15 | |
| 16 | #define CACHE_LINE_SIZE 64 |
| 17 | |
| 18 | static int curr_desc_idx = -1; |
| 19 | |
| 20 | struct cmd_desc { |
| 21 | uint32_t data_address; |
| 22 | uint32_t next_descriptor; |
| 23 | uint32_t direction:1; |
| 24 | uint32_t multi_io_mode:3; |
| 25 | uint32_t reserved1:4; |
| 26 | uint32_t fragment:1; |
| 27 | uint32_t reserved2:7; |
| 28 | uint32_t length:16; |
| 29 | //------------------------// |
| 30 | uint32_t bounce_src; |
| 31 | uint32_t bounce_dst; |
| 32 | uint32_t bounce_length; |
| 33 | uint64_t padding[5]; |
| 34 | }; |
| 35 | |
| 36 | enum qspi_mode { |
| 37 | SDR_1BIT = 1, |
| 38 | SDR_2BIT = 2, |
| 39 | SDR_4BIT = 3, |
| 40 | DDR_1BIT = 5, |
| 41 | DDR_2BIT = 6, |
| 42 | DDR_4BIT = 7, |
| 43 | }; |
| 44 | |
| 45 | enum cs_state { |
| 46 | CS_DEASSERT, |
| 47 | CS_ASSERT |
| 48 | }; |
| 49 | |
| 50 | struct xfer_cfg { |
| 51 | enum qspi_mode mode; |
| 52 | }; |
| 53 | |
| 54 | enum bus_xfer_direction { |
| 55 | MASTER_READ = 0, |
| 56 | MASTER_WRITE = 1, |
| 57 | }; |
| 58 | |
| 59 | struct { |
| 60 | struct cmd_desc descriptors[3]; |
| 61 | uint8_t buffers[3][CACHE_LINE_SIZE]; |
| 62 | } *dma = (void *)_dma_coherent; |
| 63 | |
| 64 | static void dma_transfer_chain(struct cmd_desc *chain) |
| 65 | { |
| 66 | uint32_t mstr_int_status; |
| 67 | |
| 68 | write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); |
| 69 | write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); |
| 70 | |
| 71 | while (1) { |
| 72 | mstr_int_status = read32(&sc7180_qspi->mstr_int_sts); |
| 73 | if (mstr_int_status & DMA_CHAIN_DONE) |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | static void flush_chain(void) |
| 79 | { |
| 80 | struct cmd_desc *desc = &dma->descriptors[0]; |
| 81 | uint8_t *src; |
| 82 | uint8_t *dst; |
| 83 | |
| 84 | dma_transfer_chain(desc); |
| 85 | |
| 86 | while (desc) { |
| 87 | if (desc->direction == MASTER_READ) { |
| 88 | if (desc->bounce_length == 0) |
| 89 | dcache_invalidate_by_mva( |
| 90 | (void *)(uintptr_t) desc->data_address, |
| 91 | desc->length); |
| 92 | else { |
| 93 | src = (void *)(uintptr_t) desc->bounce_src; |
| 94 | dst = (void *)(uintptr_t) desc->bounce_dst; |
| 95 | memcpy(dst, src, desc->bounce_length); |
| 96 | } |
| 97 | } |
| 98 | desc = (void *)(uintptr_t) desc->next_descriptor; |
| 99 | } |
| 100 | curr_desc_idx = -1; |
| 101 | } |
| 102 | |
| 103 | static struct cmd_desc *allocate_descriptor(void) |
| 104 | { |
| 105 | struct cmd_desc *current; |
| 106 | struct cmd_desc *next; |
| 107 | uint8_t index; |
| 108 | |
| 109 | current = (curr_desc_idx == -1) ? |
| 110 | NULL : &dma->descriptors[curr_desc_idx]; |
| 111 | |
| 112 | index = ++curr_desc_idx; |
| 113 | next = &dma->descriptors[index]; |
| 114 | |
| 115 | next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; |
| 116 | |
| 117 | next->next_descriptor = 0; |
| 118 | next->direction = MASTER_READ; |
| 119 | next->multi_io_mode = 0; |
| 120 | next->reserved1 = 0; |
satya priya | 60108fd | 2020-03-17 15:09:44 +0530 | [diff] [blame] | 121 | /* |
| 122 | * QSPI controller doesn't support transfer starts with read segment. |
| 123 | * So to support read transfers that are not preceded by write, set |
| 124 | * transfer fragment bit = 1 |
| 125 | */ |
| 126 | next->fragment = 1; |
Akash Asthana | 634c783 | 2019-07-29 18:11:15 +0530 | [diff] [blame] | 127 | next->reserved2 = 0; |
| 128 | next->length = 0; |
| 129 | next->bounce_src = 0; |
| 130 | next->bounce_dst = 0; |
| 131 | next->bounce_length = 0; |
| 132 | |
satya priya | 60108fd | 2020-03-17 15:09:44 +0530 | [diff] [blame] | 133 | if (current) |
Akash Asthana | 634c783 | 2019-07-29 18:11:15 +0530 | [diff] [blame] | 134 | current->next_descriptor = (uint32_t)(uintptr_t) next; |
Akash Asthana | 634c783 | 2019-07-29 18:11:15 +0530 | [diff] [blame] | 135 | |
| 136 | return next; |
| 137 | } |
| 138 | |
| 139 | static void cs_change(enum cs_state state) |
| 140 | { |
| 141 | gpio_set(GPIO(68), state == CS_DEASSERT); |
| 142 | } |
| 143 | |
| 144 | static void configure_gpios(void) |
| 145 | { |
| 146 | gpio_output(GPIO(68), 1); |
| 147 | |
| 148 | gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, |
| 149 | GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); |
| 150 | |
| 151 | gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, |
| 152 | GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); |
| 153 | |
| 154 | gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, |
| 155 | GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); |
| 156 | } |
| 157 | |
| 158 | static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, |
| 159 | enum qspi_mode data_mode, bool write) |
| 160 | { |
| 161 | struct cmd_desc *desc; |
| 162 | uint8_t *ptr; |
| 163 | |
| 164 | desc = allocate_descriptor(); |
| 165 | desc->direction = write; |
| 166 | desc->multi_io_mode = data_mode; |
| 167 | ptr = (void *)(uintptr_t) desc->data_address; |
| 168 | |
| 169 | if (write) { |
| 170 | memcpy(ptr, data, data_bytes); |
| 171 | } else { |
| 172 | desc->bounce_src = (uint32_t)(uintptr_t) ptr; |
| 173 | desc->bounce_dst = (uint32_t)(uintptr_t) data; |
| 174 | desc->bounce_length = data_bytes; |
| 175 | } |
| 176 | |
| 177 | desc->length = data_bytes; |
| 178 | } |
| 179 | |
| 180 | static void queue_direct_data(uint8_t *data, uint32_t data_bytes, |
| 181 | enum qspi_mode data_mode, bool write) |
| 182 | { |
| 183 | struct cmd_desc *desc; |
| 184 | |
| 185 | desc = allocate_descriptor(); |
| 186 | desc->direction = write; |
| 187 | desc->multi_io_mode = data_mode; |
| 188 | desc->data_address = (uint32_t)(uintptr_t) data; |
| 189 | desc->length = data_bytes; |
| 190 | |
| 191 | if (write) |
| 192 | dcache_clean_by_mva(data, data_bytes); |
| 193 | else |
| 194 | dcache_invalidate_by_mva(data, data_bytes); |
| 195 | } |
| 196 | |
| 197 | static void queue_data(uint8_t *data, uint32_t data_bytes, |
| 198 | enum qspi_mode data_mode, bool write) |
| 199 | { |
| 200 | uint8_t *aligned_ptr; |
| 201 | uint8_t *epilog_ptr; |
| 202 | uint32_t prolog_bytes, aligned_bytes, epilog_bytes; |
| 203 | |
| 204 | if (data_bytes == 0) |
| 205 | return; |
| 206 | |
| 207 | aligned_ptr = |
| 208 | (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); |
| 209 | |
| 210 | prolog_bytes = MIN(data_bytes, aligned_ptr - data); |
| 211 | aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); |
| 212 | epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; |
| 213 | |
| 214 | epilog_ptr = data + prolog_bytes + aligned_bytes; |
| 215 | |
| 216 | if (prolog_bytes) |
| 217 | queue_bounce_data(data, prolog_bytes, data_mode, write); |
| 218 | if (aligned_bytes) |
| 219 | queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); |
| 220 | if (epilog_bytes) |
| 221 | queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); |
| 222 | } |
| 223 | |
| 224 | static void reg_init(void) |
| 225 | { |
| 226 | uint32_t spi_mode; |
| 227 | uint32_t tx_data_oe_delay, tx_data_delay; |
| 228 | uint32_t mstr_config; |
| 229 | |
| 230 | spi_mode = 0; |
| 231 | |
| 232 | tx_data_oe_delay = 0; |
| 233 | tx_data_delay = 0; |
| 234 | |
| 235 | mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | |
| 236 | (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | |
| 237 | (spi_mode << SPI_MODE_SHIFT) | |
| 238 | (PIN_HOLDN) | |
| 239 | (FB_CLK_EN) | |
| 240 | (DMA_ENABLE) | |
| 241 | (FULL_CYCLE_MODE); |
| 242 | |
| 243 | write32(&sc7180_qspi->mstr_cfg, mstr_config); |
| 244 | write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42); |
| 245 | write32(&sc7180_qspi->mstr_int_en, 0x0); |
| 246 | write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); |
| 247 | write32(&sc7180_qspi->rd_fifo_cfg, 0x0); |
| 248 | write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO); |
| 249 | } |
| 250 | |
| 251 | void quadspi_init(uint32_t hz) |
| 252 | { |
| 253 | assert(dcache_line_bytes() == CACHE_LINE_SIZE); |
| 254 | clock_configure_qspi(hz * 4); |
| 255 | configure_gpios(); |
| 256 | reg_init(); |
| 257 | } |
| 258 | |
| 259 | int sc7180_claim_bus(const struct spi_slave *slave) |
| 260 | { |
| 261 | cs_change(CS_ASSERT); |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | void sc7180_release_bus(const struct spi_slave *slave) |
| 266 | { |
| 267 | cs_change(CS_DEASSERT); |
| 268 | } |
| 269 | |
| 270 | static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, |
| 271 | void *din, size_t in_bytes) |
| 272 | { |
| 273 | if ((out_bytes && !dout) || (in_bytes && !din) || |
| 274 | (in_bytes && out_bytes)) { |
| 275 | return -1; |
| 276 | } |
| 277 | |
| 278 | queue_data((uint8_t *) (out_bytes ? dout : din), |
| 279 | in_bytes | out_bytes, mode, !!out_bytes); |
| 280 | |
| 281 | flush_chain(); |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | int sc7180_xfer(const struct spi_slave *slave, const void *dout, |
| 287 | size_t out_bytes, void *din, size_t in_bytes) |
| 288 | { |
| 289 | return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); |
| 290 | } |
| 291 | |
| 292 | int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, |
| 293 | size_t out_bytes, void *din, size_t in_bytes) |
| 294 | { |
| 295 | return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); |
| 296 | } |