Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 4 | #include <delay.h> |
| 5 | #include <soc/addressmap.h> |
| 6 | #include <soc/clk_rst.h> |
| 7 | #include <soc/clock.h> |
| 8 | #include <soc/nvidia/tegra/i2c.h> |
| 9 | #include <soc/padconfig.h> |
| 10 | #include <soc/power.h> |
| 11 | |
| 12 | #define I2C6_PADCTL 0xC001 |
| 13 | #define DPAUX_HYBRID_PADCTL 0x545C0124 |
| 14 | #define DPAUX_HYBRID_SPARE 0x545C0134 |
| 15 | |
| 16 | static void enable_sor_periph_clocks(void) |
| 17 | { |
| 18 | clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0); |
| 19 | |
| 20 | /* Give clocks time to stabilize. */ |
| 21 | udelay(IO_STABILIZATION_DELAY); |
| 22 | } |
| 23 | |
| 24 | static void disable_sor_periph_clocks(void) |
| 25 | { |
| 26 | clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0); |
| 27 | |
| 28 | /* Give clocks time to stabilize. */ |
| 29 | udelay(IO_STABILIZATION_DELAY); |
| 30 | } |
| 31 | |
| 32 | static void unreset_sor_periphs(void) |
| 33 | { |
| 34 | clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0); |
| 35 | } |
| 36 | |
| 37 | void soc_configure_i2c6pad(void) |
| 38 | { |
| 39 | /* |
| 40 | * I2C6 on Tegra1xx requires some special init. |
| 41 | * The SOR block must be unpowergated, and a couple of |
| 42 | * display-based peripherals must be clocked and taken |
| 43 | * out of reset so that a DPAUX register can be |
| 44 | * configured to enable the I2C6 mux routing. |
| 45 | * Afterwards, we can disable clocks to the display blocks |
| 46 | * and put Host1X back in reset. DPAUX must remain out of |
| 47 | * reset and the SOR partition must remained unpowergated. |
| 48 | */ |
| 49 | soc_configure_host1x(); |
| 50 | |
Yen Lin | 13fb749 | 2015-05-29 14:36:19 -0700 | [diff] [blame] | 51 | /* enable SOR_SAFE and DPAUX_1 clocks */ |
| 52 | clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE); |
| 53 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 54 | /* Now we can write the I2C6 mux in DPAUX */ |
| 55 | write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); |
| 56 | /* Finally, power up the pads */ |
| 57 | write32((void *)DPAUX_HYBRID_SPARE, 0); |
| 58 | |
| 59 | /* |
| 60 | * Delay before turning off Host1X/DPAUX clocks. |
| 61 | * This delay is needed to keep the sequence from |
| 62 | * hanging the system. |
| 63 | */ |
| 64 | udelay(CLOCK_PLL_STABLE_DELAY_US); |
| 65 | |
| 66 | /* Stop Host1X/DPAUX clocks and reset Host1X */ |
| 67 | disable_sor_periph_clocks(); |
| 68 | clock_set_reset_l(CLK_L_HOST1X); |
| 69 | } |
| 70 | |
| 71 | void soc_configure_host1x(void) |
| 72 | { |
| 73 | power_ungate_partition(POWER_PARTID_SOR); |
| 74 | |
| 75 | /* Host1X needs a valid clock source so DPAUX can be accessed. */ |
| 76 | clock_configure_source(host1x, PLLP, 204000); |
| 77 | |
| 78 | enable_sor_periph_clocks(); |
| 79 | remove_clamps(POWER_PARTID_SOR); |
| 80 | unreset_sor_periphs(); |
| 81 | } |