Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 2 | |
| 3 | #include <arch/cache.h> |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Julius Werner | 0a8da74 | 2019-08-02 12:45:24 -0700 | [diff] [blame] | 5 | #include <bl31.h> |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 6 | #include <soc/addressmap.h> |
Andre Heider | feefcca | 2018-02-15 18:15:17 +0100 | [diff] [blame] | 7 | #include <soc/console_uart.h> |
Elyes HAOUAS | 3081855 | 2019-06-23 07:03:59 +0200 | [diff] [blame] | 8 | #include <types.h> |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 9 | |
| 10 | typedef struct bl31_plat_params { |
Andre Heider | feefcca | 2018-02-15 18:15:17 +0100 | [diff] [blame] | 11 | /* TZ memory size */ |
| 12 | uint64_t tzdram_size; |
| 13 | /* TZ memory base */ |
| 14 | uint64_t tzdram_base; |
| 15 | /* UART port ID */ |
| 16 | int uart_id; |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 17 | } bl31_plat_params_t; |
| 18 | |
| 19 | static bl31_plat_params_t t210_plat_params; |
| 20 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 21 | void *soc_get_bl31_plat_params(void) |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 22 | { |
| 23 | uintptr_t tz_base_mib; |
| 24 | size_t tz_size_mib; |
Andre Heider | feefcca | 2018-02-15 18:15:17 +0100 | [diff] [blame] | 25 | int uart_id = 0; |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 26 | |
| 27 | carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); |
| 28 | |
| 29 | assert(tz_size_mib < 4096); |
Andre Heider | feefcca | 2018-02-15 18:15:17 +0100 | [diff] [blame] | 30 | |
| 31 | switch (console_uart_get_id()) { |
| 32 | case UART_ID_NONE: |
| 33 | break; |
| 34 | case UART_ID_A: |
| 35 | uart_id = 1; |
| 36 | break; |
| 37 | case UART_ID_B: |
| 38 | uart_id = 2; |
| 39 | break; |
| 40 | case UART_ID_C: |
| 41 | uart_id = 3; |
| 42 | break; |
| 43 | case UART_ID_D: |
| 44 | uart_id = 4; |
| 45 | break; |
| 46 | case UART_ID_E: |
| 47 | uart_id = 5; |
| 48 | break; |
| 49 | } |
| 50 | |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 51 | t210_plat_params.tzdram_size = tz_size_mib * MiB; |
Andre Heider | feefcca | 2018-02-15 18:15:17 +0100 | [diff] [blame] | 52 | t210_plat_params.tzdram_base = tz_base_mib * MiB; |
| 53 | t210_plat_params.uart_id = uart_id; |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 54 | |
| 55 | dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params)); |
| 56 | |
| 57 | return &t210_plat_params; |
| 58 | } |