Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <delay.h> |
| 4 | #include <soc/addressmap.h> |
| 5 | #include <soc/clk_rst.h> |
| 6 | #include <soc/clock.h> |
| 7 | #include <soc/padconfig.h> |
| 8 | #include <soc/power.h> |
| 9 | |
| 10 | static void enable_ape_periph_clocks(void) |
| 11 | { |
| 12 | clock_enable(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE); |
| 13 | |
| 14 | /* Give clocks time to stabilize. */ |
| 15 | udelay(IO_STABILIZATION_DELAY); |
| 16 | } |
| 17 | |
| 18 | static void unreset_ape_periphs(void) |
| 19 | { |
| 20 | clock_clr_reset(0, 0, 0, CLK_V_APB2APE, 0, 0, CLK_Y_APE); |
| 21 | } |
| 22 | |
| 23 | /* |
| 24 | * Audio on Tegra210 requires some special init. |
| 25 | * The APE block must be unpowergated, and a couple of |
| 26 | * audio-based peripherals must be clocked and taken |
| 27 | * out of reset so that I2S/AXBAR/APB2APE registers can |
| 28 | * be configured to enable audio flow. |
| 29 | */ |
| 30 | |
| 31 | void soc_configure_ape(void) |
| 32 | { |
| 33 | power_ungate_partition(POWER_PARTID_APE); |
| 34 | |
| 35 | enable_ape_periph_clocks(); |
| 36 | remove_clamps(POWER_PARTID_APE); |
| 37 | unreset_ape_periphs(); |
| 38 | } |