Blame - src/soc/nvidia/tegra210/Kconfig - coreboot

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Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	1	config SOC_NVIDIA_TEGRA210
				2	bool
				3	default n
				4	select ARCH_BOOTBLOCK_ARMV4
Julius Werner	86fc11d	2015-10-09 13:37:58 -0700	[diff] [blame]	5	select BOOTBLOCK_CUSTOM
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	6	select ARCH_VERSTAGE_ARMV4
				7	select ARCH_ROMSTAGE_ARMV4
				8	select ARCH_RAMSTAGE_ARMV8_64
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	9	select GIC
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	10	select HAVE_UART_SPECIAL
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	11	select ARM64_USE_ARM_TRUSTED_FIRMWARE
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	12	select GENERIC_GPIO_LIB
				13
				14	if SOC_NVIDIA_TEGRA210
				15
Furquan Shaikh	46514c2	2020-06-11 11:59:07 -0700	[diff] [blame]	16	config MEMLAYOUT_LD_FILE
				17	string
				18	default "src/soc/nvidia/tegra210/memlayout.ld"
				19
Julius Werner	58c3938	2017-02-13 17:53:29 -0800	[diff] [blame]	20	config VBOOT
Julius Werner	1210b41	2017-03-27 19:26:32 -0700	[diff] [blame]	21	select VBOOT_STARTS_IN_BOOTBLOCK
Julius Werner	58c3938	2017-02-13 17:53:29 -0800	[diff] [blame]	22	select VBOOT_SEPARATE_VERSTAGE
Julius Werner	a2d123e	2019-11-12 15:43:12 -0800	[diff] [blame]	23	select VBOOT_RETURN_FROM_VERSTAGE
Joel Kitching	6672bd8	2019-04-10 16:06:21 +0800	[diff] [blame]	24	select VBOOT_MUST_REQUEST_DISPLAY
Martin Roth	967cd9a	2015-08-18 14:22:58 -0600	[diff] [blame]	25
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	26	config MAINBOARD_DO_DSI_INIT
				27	bool "Use dsi graphics interface"
				28	depends on MAINBOARD_DO_NATIVE_VGA_INIT
				29	default n
Nico Huber	7971582e	2017-05-20 01:07:48 +0200	[diff] [blame]	30	select HAVE_LINEAR_FRAMEBUFFER
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	31	help
				32	Initialize dsi display
				33
				34	config MAINBOARD_DO_SOR_INIT
				35	bool "Use dp graphics interface"
				36	depends on MAINBOARD_DO_NATIVE_VGA_INIT
				37	default n
Nico Huber	7971582e	2017-05-20 01:07:48 +0200	[diff] [blame]	38	select HAVE_LINEAR_FRAMEBUFFER
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	39	help
				40	Initialize dp display
				41
Martin Roth	f924aee	2016-11-11 14:24:22 -0700	[diff] [blame]	42	choice
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	43	prompt "Serial Console UART"
				44	default CONSOLE_SERIAL_TEGRA210_UARTA
Martin Roth	df02c33	2015-07-01 23:09:42 -0600	[diff] [blame]	45	depends on CONSOLE_SERIAL
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	46
				47	config CONSOLE_SERIAL_TEGRA210_UARTA
				48	bool "UARTA"
				49	help
				50	Serial console on UART A.
				51
				52	config CONSOLE_SERIAL_TEGRA210_UARTB
				53	bool "UARTB"
				54	help
				55	Serial console on UART B.
				56
				57	config CONSOLE_SERIAL_TEGRA210_UARTC
				58	bool "UARTC"
				59	help
				60	Serial console on UART C.
				61
				62	config CONSOLE_SERIAL_TEGRA210_UARTD
				63	bool "UARTD"
				64	help
				65	Serial console on UART D.
				66
				67	config CONSOLE_SERIAL_TEGRA210_UARTE
				68	bool "UARTE"
				69	help
				70	Serial console on UART E.
				71
				72	endchoice
				73
				74	config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS
				75	hex
Martin Roth	df02c33	2015-07-01 23:09:42 -0600	[diff] [blame]	76	depends on CONSOLE_SERIAL
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	77	default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA
				78	default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB
				79	default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC
				80	default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
				81	default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
				82	help
				83	Map the UART names to the respective MMIO addres.
				84
				85	config BOOTROM_SDRAM_INIT
				86	bool "SoC BootROM does SDRAM init with full BCT"
				87	default n
				88	help
				89	Use during Foster LPDDR4 bringup.
				90
				91	config TRUSTZONE_CARVEOUT_SIZE_MB
				92	hex "Size of Trust Zone region"
				93	default 0x14
				94	help
				95	Size of Trust Zone area in MiB to reserve in memory map.
				96
Furquan Shaikh	3ae5044	2015-07-07 21:35:56 -0700	[diff] [blame]	97	config TTB_SIZE_MB
				98	hex "Size of TTB"
				99	default 0x4
				100	help
				101	Maximum size of Translation Table Buffer in MiB.
				102
				103	config SEC_COMPONENT_SIZE_MB
				104	hex "Size of resident EL3 components"
				105	default 0x10
				106	help
				107	Maximum size of resident EL3 components in MiB including BL31 and
				108	Secure OS.
				109
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	110	# Default to 700MHz. This value is based on nv bootloader setting.
				111	config PLLX_KHZ
Martin Roth	45895f1	2015-07-01 19:38:29 -0600	[diff] [blame]	112	int
				113	default 700000
Patrick Georgi	40a3e32	2015-06-22 19:41:29 +0200	[diff] [blame]	114
				115	config HAVE_MTC
				116	bool "Add external Memory controller Training Code binary"
				117	default n
				118	depends on USE_BLOBS
				119	help
				120	Select this option to add emc training firmware
				121
				122	if HAVE_MTC
				123
				124	config MTC_FILE
				125	string "tegra mtc firmware filename"
				126	default "tegra_mtc.bin"
				127	help
				128	The filename of the mtc firmware
				129
				130	config MTC_DIRECTORY
				131	string "Directory where MTC firmware file is located"
				132	default "."
				133	help
				134	Path to directory where MTC firmware file is located.
				135
				136	config MTC_ADDRESS
				137	hex
				138	default 0x81000000
				139	help
				140	The DRAM location where MTC firmware to be loaded in. This location
				141	needs to be consistent with the location defined in tegra_mtc.ld
				142
				143	endif # HAVE_MTC
				144
Vladimir Serbinenko	5226266	2015-10-11 02:17:21 +0200	[diff] [blame]	145	endif # SOC_NVIDIA_TEGRA210