Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 4 | #include <delay.h> |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 5 | |
| 6 | #include <soc/addressmap.h> |
| 7 | #include <soc/infracfg.h> |
| 8 | #include <soc/mcucfg.h> |
| 9 | #include <soc/pll.h> |
| 10 | |
| 11 | enum mux_id { |
| 12 | TOP_AXI_SEL = 0, |
| 13 | TOP_MM_SEL, |
| 14 | TOP_IMG_SEL, |
| 15 | TOP_CAM_SEL, |
| 16 | TOP_DSP_SEL, |
| 17 | TOP_DSP1_SEL, |
| 18 | TOP_DSP2_SEL, |
| 19 | TOP_IPU_IF_SEL, |
| 20 | TOP_MFG_SEL, |
| 21 | TOP_MFG_52M_SEL, |
| 22 | TOP_CAMTG_SEL, |
| 23 | TOP_CAMTG2_SEL, |
| 24 | TOP_CAMTG3_SEL, |
| 25 | TOP_CAMTG4_SEL, |
| 26 | TOP_UART_SEL, |
| 27 | TOP_SPI_SEL, |
| 28 | TOP_MSDC50_0_HCLK_SEL, |
| 29 | TOP_MSDC50_0_SEL, |
| 30 | TOP_MSDC30_1_SEL, |
| 31 | TOP_MSDC30_2_SEL, |
| 32 | TOP_AUDIO_SEL, |
| 33 | TOP_AUD_INTBUS_SEL, |
| 34 | TOP_PMICSPI_SEL, |
| 35 | TOP_PWRAP_ULPOSC_SEL, |
| 36 | TOP_ATB_SEL, |
| 37 | TOP_PWRMCU_SEL, |
| 38 | TOP_DPI0_SEL, |
| 39 | TOP_SCAM_SEL, |
| 40 | TOP_DISP_PWM_SEL, |
| 41 | TOP_USB_TOP_SEL, |
| 42 | TOP_SSUSB_XHCI_SEL, |
| 43 | TOP_SPM_SEL, |
| 44 | TOP_I2C_SEL, |
| 45 | TOP_SCP_SEL, |
| 46 | TOP_SENINF_SEL, |
| 47 | TOP_DXCC_SEL, |
| 48 | TOP_AUD_ENGEN1_SEL, |
| 49 | TOP_AUD_ENGEN2_SEL, |
| 50 | TOP_AES_UFSFDE_SEL, |
| 51 | TOP_UFS_SEL, |
| 52 | TOP_AUD_1_SEL, |
| 53 | TOP_AUD_2_SEL, |
| 54 | TOP_NR_MUX |
| 55 | }; |
| 56 | |
| 57 | #define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift) \ |
| 58 | [_id] = { \ |
| 59 | .reg = &mtk_topckgen->_reg, \ |
| 60 | .mux_shift = _mux_shift, \ |
| 61 | .mux_width = _mux_width, \ |
| 62 | .upd_reg = &mtk_topckgen->_upd_reg, \ |
| 63 | .upd_shift = _upd_shift, \ |
| 64 | } |
| 65 | |
| 66 | static const struct mux muxes[] = { |
| 67 | /* CLK_CFG_0 */ |
| 68 | MUX(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0), |
| 69 | MUX(TOP_MM_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1), |
| 70 | MUX(TOP_IMG_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2), |
| 71 | MUX(TOP_CAM_SEL, clk_cfg_0, 24, 4, clk_cfg_update, 3), |
| 72 | /* CLK_CFG_1 */ |
| 73 | MUX(TOP_DSP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), |
| 74 | MUX(TOP_DSP1_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), |
| 75 | MUX(TOP_DSP2_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), |
| 76 | MUX(TOP_IPU_IF_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), |
| 77 | /* CLK_CFG_2 */ |
| 78 | MUX(TOP_MFG_SEL, clk_cfg_2, 0, 2, clk_cfg_update, 8), |
| 79 | MUX(TOP_MFG_52M_SEL, clk_cfg_2, 8, 2, clk_cfg_update, 9), |
| 80 | MUX(TOP_CAMTG_SEL, clk_cfg_2, 16, 3, clk_cfg_update, 10), |
| 81 | MUX(TOP_CAMTG2_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11), |
| 82 | /* CLK_CFG_3 */ |
| 83 | MUX(TOP_CAMTG3_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12), |
| 84 | MUX(TOP_CAMTG4_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13), |
| 85 | MUX(TOP_UART_SEL, clk_cfg_3, 16, 1, clk_cfg_update, 14), |
| 86 | MUX(TOP_SPI_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15), |
| 87 | /* CLK_CFG_4 */ |
| 88 | MUX(TOP_MSDC50_0_HCLK_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16), |
| 89 | MUX(TOP_MSDC50_0_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17), |
| 90 | MUX(TOP_MSDC30_1_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18), |
| 91 | MUX(TOP_MSDC30_2_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19), |
| 92 | /* CLK_CFG_5 */ |
| 93 | MUX(TOP_AUDIO_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20), |
| 94 | MUX(TOP_AUD_INTBUS_SEL, clk_cfg_5, 8, 2, clk_cfg_update, 21), |
| 95 | MUX(TOP_PMICSPI_SEL, clk_cfg_5, 16, 2, clk_cfg_update, 22), |
| 96 | MUX(TOP_PWRAP_ULPOSC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23), |
| 97 | /* CLK_CFG_6 */ |
| 98 | MUX(TOP_ATB_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24), |
| 99 | MUX(TOP_PWRMCU_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25), |
| 100 | MUX(TOP_DPI0_SEL, clk_cfg_6, 16, 4, clk_cfg_update, 26), |
| 101 | MUX(TOP_SCAM_SEL, clk_cfg_6, 24, 1, clk_cfg_update, 27), |
| 102 | /* CLK_CFG_7 */ |
| 103 | MUX(TOP_DISP_PWM_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28), |
| 104 | MUX(TOP_USB_TOP_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29), |
| 105 | MUX(TOP_SSUSB_XHCI_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30), |
| 106 | MUX(TOP_SPM_SEL, clk_cfg_7, 24, 1, clk_cfg_update1, 0), |
| 107 | /* CLK_CFG_8 */ |
| 108 | MUX(TOP_I2C_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), |
| 109 | MUX(TOP_SCP_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), |
| 110 | MUX(TOP_SENINF_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3), |
| 111 | MUX(TOP_DXCC_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4), |
| 112 | /* CLK_CFG_9 */ |
| 113 | MUX(TOP_AUD_ENGEN1_SEL, clk_cfg_9, 0, 2, clk_cfg_update1, 5), |
| 114 | MUX(TOP_AUD_ENGEN2_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 6), |
| 115 | MUX(TOP_AES_UFSFDE_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7), |
| 116 | MUX(TOP_UFS_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8), |
| 117 | /* CLK_CFG_10 */ |
| 118 | MUX(TOP_AUD_1_SEL, clk_cfg_10, 0, 1, clk_cfg_update1, 9), |
| 119 | MUX(TOP_AUD_2_SEL, clk_cfg_10, 8, 1, clk_cfg_update1, 10), |
| 120 | }; |
| 121 | |
| 122 | struct mux_sel { |
| 123 | enum mux_id id; |
| 124 | u32 sel; |
| 125 | }; |
| 126 | |
| 127 | static const struct mux_sel mux_sels[] = { |
| 128 | /* CLK_CFG_0 */ |
| 129 | { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7 */ |
| 130 | { .id = TOP_MM_SEL, .sel = 1 }, /* 1: mmpll_d7 */ |
| 131 | { .id = TOP_IMG_SEL, .sel = 1 }, /* 1: mmpll_d6 */ |
| 132 | { .id = TOP_CAM_SEL, .sel = 1 }, /* 1: mainpll_d2 */ |
| 133 | /* CLK_CFG_1 */ |
| 134 | { .id = TOP_DSP_SEL, .sel = 1 }, /* 1: mmpll_d6 */ |
| 135 | { .id = TOP_DSP1_SEL, .sel = 1 }, /* 1: mmpll_d6 */ |
| 136 | { .id = TOP_DSP2_SEL, .sel = 1 }, /* 1: mmpll_d6 */ |
| 137 | { .id = TOP_IPU_IF_SEL, .sel = 1 }, /* 1: mmpll_d6 */ |
| 138 | /* CLK_CFG_2 */ |
| 139 | { .id = TOP_MFG_SEL, .sel = 1 }, /* 1: mfgpll_ck */ |
| 140 | { .id = TOP_MFG_52M_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */ |
| 141 | { .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univ_192m_d8 */ |
| 142 | { .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univ_192m_d8 */ |
| 143 | /* CLK_CFG_3 */ |
| 144 | { .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univ_192m_d8 */ |
| 145 | { .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univ_192m_d8 */ |
| 146 | { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ |
| 147 | { .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */ |
| 148 | /* CLK_CFG_4 */ |
| 149 | { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ |
| 150 | { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ |
| 151 | { .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ |
| 152 | { .id = TOP_MSDC30_2_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */ |
| 153 | /* CLK_CFG_5 */ |
| 154 | { .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */ |
| 155 | { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d2_d4 */ |
| 156 | { .id = TOP_PMICSPI_SEL, .sel = 0 }, /* 0: clk26m */ |
| 157 | { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: clk26m */ |
| 158 | /* CLK_CFG_6 */ |
| 159 | { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ |
| 160 | { .id = TOP_PWRMCU_SEL, .sel = 2 }, /* 2: mainpll_d2_d2 */ |
| 161 | { .id = TOP_DPI0_SEL, .sel = 1 }, /* 1: tvdpll_d2 */ |
| 162 | { .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */ |
| 163 | /* CLK_CFG_7 */ |
| 164 | { .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ |
| 165 | { .id = TOP_USB_TOP_SEL, .sel = 3 }, /* 3: univpll_d5_d2 */ |
| 166 | { .id = TOP_SSUSB_XHCI_SEL, .sel = 3 }, /* 3: univpll_d5_d2 */ |
| 167 | { .id = TOP_SPM_SEL, .sel = 1 }, /* 1: mainpll_d2_d8 */ |
| 168 | /* CLK_CFG_8 */ |
| 169 | { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ |
| 170 | { .id = TOP_SCP_SEL, .sel = 1 }, /* 1: univpll_d2_d8 */ |
| 171 | { .id = TOP_SENINF_SEL, .sel = 1 }, /* 1: univpll_d2_d2 */ |
| 172 | { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ |
| 173 | /* CLK_CFG_9 */ |
| 174 | { .id = TOP_AUD_ENGEN1_SEL, .sel = 3 }, /* 3: apll1_d8 */ |
| 175 | { .id = TOP_AUD_ENGEN2_SEL, .sel = 3 }, /* 3: apll2_d8 */ |
| 176 | { .id = TOP_AES_UFSFDE_SEL, .sel = 3 }, /* 3: mainpll_d3 */ |
| 177 | { .id = TOP_UFS_SEL, .sel = 1 }, /* 1: mainpll_d2_d4 */ |
| 178 | /* CLK_CFG_10 */ |
| 179 | { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 180 | { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ |
| 181 | }; |
| 182 | |
| 183 | #define MMPLL_RSTB_SHIFT (23) |
| 184 | |
| 185 | enum pll_id { |
| 186 | APMIXED_ARMPLL_LL, |
| 187 | APMIXED_ARMPLL_L, |
| 188 | APMIXED_CCIPLL, |
| 189 | APMIXED_MAINPLL, |
| 190 | APMIXED_UNIVPLL, |
| 191 | APMIXED_MSDCPLL, |
| 192 | APMIXED_MMPLL, |
| 193 | APMIXED_MFGPLL, |
| 194 | APMIXED_TVDPLL, |
| 195 | APMIXED_APLL1, |
| 196 | APMIXED_APLL2, |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 197 | APMIXED_MPLL, |
| 198 | APMIXED_PLL_MAX |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | const u32 pll_div_rate[] = { |
| 202 | 3800UL * MHz, |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 203 | 1900 * MHz, |
| 204 | 950 * MHz, |
| 205 | 475 * MHz, |
| 206 | 237500 * KHz, |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 207 | 0, |
| 208 | }; |
| 209 | |
| 210 | static const struct pll plls[] = { |
| 211 | PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_pwr_con0, |
| 212 | PLL_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, |
| 213 | pll_div_rate), |
| 214 | PLL(APMIXED_ARMPLL_L, armpll_l_con0, armpll_l_pwr_con0, |
| 215 | PLL_RSTB_SHIFT, 22, armpll_l_con1, 24, armpll_l_con1, 0, |
| 216 | pll_div_rate), |
| 217 | PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_pwr_con0, |
| 218 | PLL_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, |
| 219 | pll_div_rate), |
| 220 | PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, |
| 221 | PLL_RSTB_SHIFT, 22, mainpll_con1, 24, mainpll_con1, 0, |
| 222 | pll_div_rate), |
| 223 | PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, |
| 224 | PLL_RSTB_SHIFT, 22, univpll_con1, 24, univpll_con1, 0, |
| 225 | pll_div_rate), |
| 226 | PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, |
| 227 | NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, |
| 228 | pll_div_rate), |
| 229 | PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, |
| 230 | MMPLL_RSTB_SHIFT, 22, mmpll_con1, 24, mmpll_con1, 0, |
| 231 | pll_div_rate), |
| 232 | PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_pwr_con0, |
| 233 | NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, |
| 234 | pll_div_rate), |
| 235 | PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, |
| 236 | NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, |
| 237 | pll_div_rate), |
| 238 | PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, |
| 239 | NO_RSTB_SHIFT, 32, apll1_con0, 1, apll1_con1, 0, |
| 240 | pll_div_rate), |
| 241 | PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, |
| 242 | NO_RSTB_SHIFT, 32, apll2_con0, 1, apll2_con1, 0, |
| 243 | pll_div_rate), |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 244 | PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, |
| 245 | NO_RSTB_SHIFT, 22, mpll_con1, 24, mpll_con1, 0, |
| 246 | pll_div_rate), |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | struct rate { |
| 250 | enum pll_id id; |
| 251 | u32 rate; |
| 252 | }; |
| 253 | |
| 254 | static const struct rate rates[] = { |
| 255 | { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, |
| 256 | { .id = APMIXED_ARMPLL_L, .rate = ARMPLL_L_HZ }, |
| 257 | { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, |
| 258 | { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, |
| 259 | { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, |
| 260 | { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, |
| 261 | { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, |
| 262 | { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, |
| 263 | { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, |
| 264 | { .id = APMIXED_APLL1, .rate = APLL1_HZ }, |
| 265 | { .id = APMIXED_APLL2, .rate = APLL2_HZ }, |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 266 | { .id = APMIXED_MPLL, .rate = MPLL_HZ }, |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | void pll_set_pcw_change(const struct pll *pll) |
| 270 | { |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 271 | setbits32(pll->div_reg, PLL_PCW_CHG); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | void mt_pll_init(void) |
| 275 | { |
| 276 | int i; |
| 277 | |
| 278 | /* enable univpll & mainpll div */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 279 | setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 280 | |
| 281 | /* enable clock square1 low-pass filter */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 282 | setbits32(&mtk_apmixed->ap_pll_con0, 0x2); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 283 | |
| 284 | /* xPLL PWR ON */ |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 285 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 286 | setbits32(plls[i].pwr_reg, PLL_PWR_ON); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 287 | |
| 288 | udelay(PLL_PWR_ON_DELAY); |
| 289 | |
| 290 | /* xPLL ISO Disable */ |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 291 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 292 | clrbits32(plls[i].pwr_reg, PLL_ISO); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 293 | |
| 294 | udelay(PLL_ISO_DELAY); |
| 295 | |
| 296 | /* xPLL Frequency Set */ |
| 297 | for (i = 0; i < ARRAY_SIZE(rates); i++) |
| 298 | pll_set_rate(&plls[rates[i].id], rates[i].rate); |
| 299 | |
| 300 | /* AUDPLL Tuner Frequency Set */ |
| 301 | write32(&mtk_apmixed->apll1_con2, |
| 302 | read32(&mtk_apmixed->apll1_con1) + 1); |
| 303 | write32(&mtk_apmixed->apll2_con2, |
| 304 | read32(&mtk_apmixed->apll2_con1) + 1); |
| 305 | |
| 306 | /* xPLL Frequency Enable */ |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 307 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 308 | setbits32(plls[i].reg, PLL_EN); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 309 | |
| 310 | /* wait for PLL stable */ |
| 311 | udelay(PLL_EN_DELAY); |
| 312 | |
| 313 | /* xPLL DIV RSTB */ |
Tristan Shieh | 022f76b | 2018-09-14 11:12:14 +0800 | [diff] [blame] | 314 | for (i = 0; i < APMIXED_PLL_MAX; i++) { |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 315 | if (plls[i].rstb_shift != NO_RSTB_SHIFT) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 316 | setbits32(plls[i].reg, 1 << plls[i].rstb_shift); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | /* MCUCFG CLKMUX */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 320 | clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1); |
| 321 | clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1); |
| 322 | clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 323 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 324 | clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 325 | MUX_SRC_ARMPLL); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 326 | clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK, |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 327 | MUX_SRC_ARMPLL); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 328 | clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK, |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 329 | MUX_SRC_ARMPLL); |
| 330 | |
| 331 | /* enable infrasys DCM */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 332 | setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); |
| 333 | clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, |
Weiyi Lu | e621d8f | 2019-03-19 13:39:12 +0800 | [diff] [blame] | 334 | DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 335 | setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); |
| 336 | clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); |
| 337 | clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl, |
Weiyi Lu | e621d8f | 2019-03-19 13:39:12 +0800 | [diff] [blame] | 338 | DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 339 | |
Qii Wang | d569845 | 2019-02-20 14:57:28 +0800 | [diff] [blame] | 340 | /* enable [11] for change i2c module source clock to TOPCKGEN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 341 | setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); |
Qii Wang | d569845 | 2019-02-20 14:57:28 +0800 | [diff] [blame] | 342 | |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 343 | /* |
| 344 | * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! |
| 345 | */ |
| 346 | for (i = 0; i < ARRAY_SIZE(mux_sels); i++) |
| 347 | mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); |
| 348 | |
| 349 | /* enable [14] dramc_pll104m_ck */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 350 | setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); |
Jiaxin Yu | 5a69491 | 2019-04-25 17:14:26 +0800 | [diff] [blame] | 351 | |
| 352 | /* enable audio clock */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 353 | setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); |
Jiaxin Yu | 5a69491 | 2019-04-25 17:14:26 +0800 | [diff] [blame] | 354 | |
| 355 | /* enable intbus clock */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 356 | setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); |
Jiaxin Yu | 5a69491 | 2019-04-25 17:14:26 +0800 | [diff] [blame] | 357 | |
| 358 | /* enable infra clock */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 359 | setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); |
Jiaxin Yu | 5a69491 | 2019-04-25 17:14:26 +0800 | [diff] [blame] | 360 | |
| 361 | /* enable mtkaif 26m clock */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 362 | setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); |
Weiyi Lu | 60e1fcb | 2018-06-01 14:58:54 +0800 | [diff] [blame] | 363 | } |
Tristan Shieh | 3d96f60 | 2019-04-26 11:58:30 +0800 | [diff] [blame] | 364 | |
Weiyi Lu | 86b3bf1 | 2020-06-19 15:28:55 +0800 | [diff] [blame] | 365 | void mt_pll_raise_little_cpu_freq(u32 freq) |
Tristan Shieh | 3d96f60 | 2019-04-26 11:58:30 +0800 | [diff] [blame] | 366 | { |
Weiyi Lu | 38779e6 | 2020-05-06 11:05:15 +0800 | [diff] [blame] | 367 | /* enable [4] intermediate clock armpll_divider_pll1_ck */ |
| 368 | setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
| 369 | |
| 370 | /* switch ca53 clock source to intermediate clock */ |
| 371 | clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, |
| 372 | MUX_SRC_DIV_PLL1); |
| 373 | |
| 374 | /* disable armpll_ll frequency output */ |
| 375 | clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); |
| 376 | |
| 377 | /* raise armpll_ll frequency */ |
Tristan Shieh | 3d96f60 | 2019-04-26 11:58:30 +0800 | [diff] [blame] | 378 | pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); |
Weiyi Lu | 38779e6 | 2020-05-06 11:05:15 +0800 | [diff] [blame] | 379 | |
| 380 | /* enable armpll_ll frequency output */ |
| 381 | setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); |
| 382 | udelay(PLL_EN_DELAY); |
| 383 | |
| 384 | /* switch ca53 clock source back to armpll_ll */ |
| 385 | clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, |
| 386 | MUX_SRC_ARMPLL); |
| 387 | |
| 388 | /* disable [4] intermediate clock armpll_divider_pll1_ck */ |
| 389 | clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
Tristan Shieh | 3d96f60 | 2019-04-26 11:58:30 +0800 | [diff] [blame] | 390 | } |