Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 4 | #include <cbmem.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 8 | #include <elog.h> |
| 9 | #include <soc/iomap.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 10 | #include <soc/pm.h> |
| 11 | #include <stdint.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 12 | |
| 13 | static void log_power_and_resets(const struct chipset_power_state *ps) |
| 14 | { |
| 15 | if (ps->gen_pmcon1 & PWR_FLR) { |
| 16 | elog_add_event(ELOG_TYPE_POWER_FAIL); |
| 17 | elog_add_event(ELOG_TYPE_PWROK_FAIL); |
| 18 | } |
| 19 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 20 | if (ps->gen_pmcon1 & SUS_PWR_FLR) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 23 | if (ps->gen_pmcon1 & RPS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | elog_add_event(ELOG_TYPE_RTC_RESET); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 25 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 26 | if (ps->tco_sts & SECOND_TO_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | elog_add_event(ELOG_TYPE_TCO_RESET); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 28 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 29 | if (ps->pm1_sts & PRBTNOR_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 31 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | if (ps->gen_pmcon1 & SRS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | elog_add_event(ELOG_TYPE_RESET_BUTTON); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 34 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 35 | if (ps->gen_pmcon1 & GEN_RST_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 36 | elog_add_event(ELOG_TYPE_SYSTEM_RESET); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | static void log_wake_events(const struct chipset_power_state *ps) |
| 40 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 41 | const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | |
| 42 | PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; |
| 43 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 44 | uint32_t gpe0_sts; |
| 45 | uint32_t gpio_mask; |
| 46 | int i; |
| 47 | |
| 48 | /* Mask off disabled events. */ |
| 49 | gpe0_sts = ps->gpe0_sts & ps->gpe0_en; |
| 50 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 51 | if (ps->pm1_sts & WAK_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 52 | elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 53 | acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 55 | if (ps->pm1_sts & PWRBTN_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 57 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 58 | if (ps->pm1_sts & RTC_STS) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 59 | elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 60 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 61 | if (gpe0_sts & PME_B0_EN) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 63 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 64 | if (gpe0_sts & pcie_wake_mask) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 66 | |
| 67 | gpio_mask = SUS_GPIO_STS0; |
| 68 | i = 0; |
| 69 | while (gpio_mask) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 70 | if (gpio_mask & gpe0_sts) |
Aaron Durbin | aa90203 | 2020-08-17 09:37:13 -0600 | [diff] [blame] | 71 | elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 72 | gpio_mask <<= 1; |
| 73 | i++; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | void southcluster_log_state(void) |
| 78 | { |
| 79 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 80 | |
| 81 | if (ps == NULL) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 82 | printk(BIOS_DEBUG, |
| 83 | "Not logging power state information. Power state not found in cbmem.\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 84 | return; |
| 85 | } |
| 86 | |
| 87 | log_power_and_resets(ps); |
| 88 | log_wake_events(ps); |
| 89 | } |