blob: ab0182c0b2d4b1686d0a71e4bc94c276be84df1e [file] [log] [blame]
Nico Huber4f32b642018-10-05 23:40:21 +02001config MISSING_BOARD_RESET
2 bool
3 help
4 Selected by boards that don't provide a do_board_reset()
5 implementation. This activates a stub that logs the missing
6 board reset and halts execution.
7
Nico Huber3db76532017-05-18 18:07:34 +02008config NO_EDID_FILL_FB
9 bool
10 default y if !MAINBOARD_DO_NATIVE_VGA_INIT
11 help
12 Don't include default fill_lb_framebuffer() implementation. Select
13 this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
14 its own fill_lb_framebuffer() implementation.
Nico Huberbc652b92017-07-17 23:39:02 +020015
16config RAMSTAGE_ADA
17 bool
18 help
19 Selected by features that use Ada code in ramstage.
20
21config RAMSTAGE_LIBHWBASE
22 bool
23 select RAMSTAGE_ADA
24 help
25 Selected by features that require `libhwbase` in ramstage.
26
Patrick Rudolph666c1722018-04-03 09:57:33 +020027config FLATTENED_DEVICE_TREE
28 bool
29 help
30 Selected by features that require to parse and manipulate a flattened
31 devicetree in ramstage.
32
Michael Niewöhner87cc8892020-09-07 14:26:09 +020033config HAVE_SPD_IN_CBFS
Elyes HAOUASfc46ad82019-05-19 11:49:27 +020034 bool
35 help
36 If enabled, add support for adding spd.hex files in cbfs as spd.bin
Michael Niewöhner856731d2020-09-07 13:26:51 +020037 and locating it runtime to load SPD.
Elyes HAOUASfc46ad82019-05-19 11:49:27 +020038
39config DIMM_MAX
40 int
41 default 4
42 help
43 Total number of memory DIMM slots available on motherboard.
44 It is multiplication of number of channel to number of DIMMs per
45 channel
46
47config DIMM_SPD_SIZE
48 int
49 default 256
50 help
51 Total SPD size that will be used for DIMM.
52 Ex: DDR3 256, DDR4 512.
53
54config SPD_READ_BY_WORD
55 bool
56
Nico Huberbc652b92017-07-17 23:39:02 +020057if RAMSTAGE_LIBHWBASE
58
59config HWBASE_DYNAMIC_MMIO
60 def_bool y
61
Nico Huber625160f2017-07-17 23:42:33 +020062config HWBASE_DEFAULT_MMCONF
63 hex
64 default MMCONF_BASE_ADDRESS
65
66config HWBASE_DIRECT_PCIDEV
67 def_bool y
68
Nico Huberbc652b92017-07-17 23:39:02 +020069endif
Julius Werner7fc92862019-11-18 13:01:06 -080070
71config NO_FMAP_CACHE
72 bool
73 help
74 If your platform really doesn't want to use an FMAP cache (e.g. due to
75 space constraints), you can select this to disable warnings and save
76 a bit more code.
Furquan Shaikh5cc41f22020-05-11 12:11:27 -070077
78config ESPI_DEBUG
79 bool
80 help
81 This option enables eSPI library helper functions for displaying debug
82 information.
Julius Werner1e37c9c2019-12-11 17:09:39 -080083
84config NO_CBFS_MCACHE
85 bool
Julius Werner1e37c9c2019-12-11 17:09:39 -080086 help
87 Disables the CBFS metadata cache. This means that your platform does
88 not need to provide a CBFS_MCACHE section in memlayout and can save
89 the associated CAR/SRAM size. In that case every single CBFS file
90 lookup must re-read the same CBFS directory entries from flash to find
91 the respective file.
92
93config CBFS_MCACHE_RW_PERCENTAGE
94 int
95 depends on VBOOT && !NO_CBFS_MCACHE
96 default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only
97 default 50
98 help
99 The amount of the CBFS_MCACHE area that's used for the RW CBFS, in
100 percent from 0 to 100. The remaining area will be used for the RO
101 CBFS. Default is an even 50/50 split. When VBOOT is disabled, this
102 will automatically be 0 (meaning the whole MCACHE is used for RO).