Angel Pons | 32859fc | 2020-04-02 23:48:27 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 2 | |
Martin Roth | 7a4c021 | 2017-07-23 21:05:24 -0600 | [diff] [blame] | 3 | #ifndef __SPD_DDR2_H__ |
| 4 | #define __SPD_DDR2_H__ |
| 5 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 6 | /* SPDs for DDR2 SDRAM */ |
| 7 | #define SPD_MEM_TYPE 2 |
| 8 | #define SPD_MEM_TYPE_SDRAM_DDR 0x07 |
| 9 | #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 |
| 10 | |
| 11 | #define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ |
Elyes HAOUAS | c8d24dd | 2016-06-15 21:13:07 +0200 | [diff] [blame] | 12 | #define SPD_DIMM_TYPE_RDIMM 0x01 |
| 13 | #define SPD_DIMM_TYPE_UDIMM 0x02 |
| 14 | #define SPD_DIMM_TYPE_SODIMM 0x04 |
| 15 | #define SPD_72B_SO_CDIMM 0x06 |
| 16 | #define SPD_72B_SO_RDIMM 0x07 |
| 17 | #define SPD_DIMM_TYPE_uDIMM 0x08 |
| 18 | #define SPD_DIMM_TYPE_mRDIMM 0x10 |
| 19 | #define SPD_DIMM_TYPE_mUDIMM 0x20 |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 20 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 21 | #define SPD_MOD_ATTRIB 21 |
| 22 | #define SPD_MOD_ATTRIB_DIFCK 0x20 |
| 23 | #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ |
| 24 | #define SPD_MOD_ATTRIB_PROBE 0x40 |
| 25 | |
| 26 | #define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ |
| 27 | #define SPD_DIMM_CONF_TYPE 11 |
| 28 | #define SPD_DIMM_CONF_TYPE_ECC 0x02 |
| 29 | #define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */ |
| 30 | |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 31 | #define SPD_CAS_LAT_MIN_X_1 23 |
| 32 | #define SPD_CAS_LAT_MAX_X_1 24 |
| 33 | #define SPD_CAS_LAT_MIN_X_2 25 |
| 34 | #define SPD_CAS_LAT_MAX_X_2 26 |
| 35 | |
| 36 | #define SPD_BURST_LENGTHS 16 |
| 37 | #define SPD_BURST_LENGTHS_4 (1<<2) |
| 38 | #define SPD_BURST_LENGTHS_8 (1<<3) |
| 39 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 40 | #define SPD_ROW_NUM 3 /* Number of Row addresses */ |
| 41 | #define SPD_COL_NUM 4 /* Number of Column addresses */ |
| 42 | #define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on |
| 43 | SDRAM device, it could be 0x4, 0x8, so address |
| 44 | lines for that would be 2, and 3 */ |
| 45 | |
Elyes HAOUAS | 5f73e22 | 2020-01-15 21:13:45 +0100 | [diff] [blame] | 46 | /* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planar), |
Lee Leahy | 6a566d7 | 2017-03-07 17:45:12 -0800 | [diff] [blame] | 47 | * Height bit[7:5] |
| 48 | */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 49 | #define SPD_MOD_ATTRIB_RANK 5 |
| 50 | #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 |
| 51 | #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 |
| 52 | #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 |
| 53 | #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 |
| 54 | #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 |
| 55 | |
| 56 | #define SPD_RANK_SIZE 31 /* Only one bit is set */ |
| 57 | #define SPD_RANK_SIZE_1GB (1<<0) |
| 58 | #define SPD_RANK_SIZE_2GB (1<<1) |
| 59 | #define SPD_RANK_SIZE_4GB (1<<2) |
| 60 | #define SPD_RANK_SIZE_8GB (1<<3) |
| 61 | #define SPD_RANK_SIZE_16GB (1<<4) |
| 62 | #define SPD_RANK_SIZE_128MB (1<<5) |
| 63 | #define SPD_RANK_SIZE_256MB (1<<6) |
| 64 | #define SPD_RANK_SIZE_512MB (1<<7) |
| 65 | |
Lee Leahy | 6a566d7 | 2017-03-07 17:45:12 -0800 | [diff] [blame] | 66 | /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ |
| 67 | #define SPD_DATA_WIDTH 6 |
| 68 | /* Primary SDRAM Width, it could be 0x08 or 0x10 */ |
| 69 | #define SPD_PRI_WIDTH 13 |
| 70 | /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ |
| 71 | #define SPD_ERR_WIDTH 14 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 72 | |
| 73 | #define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ |
| 74 | #define SPD_CAS_LAT_2 (1<<2) |
| 75 | #define SPD_CAS_LAT_3 (1<<3) |
| 76 | #define SPD_CAS_LAT_4 (1<<4) |
| 77 | #define SPD_CAS_LAT_5 (1<<5) |
| 78 | #define SPD_CAS_LAT_6 (1<<6) |
Elyes HAOUAS | d450609 | 2016-05-26 19:53:29 +0200 | [diff] [blame] | 79 | #define SPD_CAS_LAT_7 (1<<7) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 80 | |
Lee Leahy | 6a566d7 | 2017-03-07 17:45:12 -0800 | [diff] [blame] | 81 | /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) |
| 82 | * + (val & 3) * 0.25)ns |
| 83 | */ |
| 84 | #define SPD_TRP 27 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 85 | #define SPD_TRRD 28 |
| 86 | #define SPD_TRCD 29 |
| 87 | #define SPD_TRAS 30 |
Lee Leahy | 6a566d7 | 2017-03-07 17:45:12 -0800 | [diff] [blame] | 88 | #define SPD_TWR 36 /* x */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 89 | #define SPD_TWTR 37 /* x */ |
| 90 | #define SPD_TRTP 38 /* x */ |
| 91 | |
Stefan Reinauer | aeba92a | 2009-04-17 08:37:18 +0000 | [diff] [blame] | 92 | #define SPD_EX_TRC_TRFC 40 |
Lee Leahy | 6a566d7 | 2017-03-07 17:45:12 -0800 | [diff] [blame] | 93 | /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] |
| 94 | * ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0} |
| 95 | */ |
| 96 | #define SPD_TRC 41 |
| 97 | /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] |
| 98 | * + (val40 & 1)*256 |
| 99 | */ |
| 100 | #define SPD_TRFC 42 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 101 | |
| 102 | #define SPD_TREF 12 |
Martin Roth | 7a4c021 | 2017-07-23 21:05:24 -0600 | [diff] [blame] | 103 | |
| 104 | #endif /* __SPD_DDR2_H__ */ |