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Angel Ponsc74dae92020-04-02 23:48:16 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Yinghai Lu304f24c2005-07-08 02:56:47 +00002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02006#include <device/pci_ops.h>
Yinghai Lu304f24c2005-07-08 02:56:47 +00007#include <device/cardbus.h>
8
Uwe Hermannd453dd02010-10-18 00:00:57 +00009/*
10 * I don't think this code is quite correct but it is close.
Yinghai Lu304f24c2005-07-08 02:56:47 +000011 * Anyone with a cardbus bridge and a little time should be able
12 * to make it usable quickly. -- Eric Biederman 24 March 2005
13 */
14
15/*
Uwe Hermannd453dd02010-10-18 00:00:57 +000016 * IO should be max 256 bytes. However, since we may have a P2P bridge below
17 * a cardbus bridge, we need 4K.
Yinghai Lu304f24c2005-07-08 02:56:47 +000018 */
Uwe Hermannd453dd02010-10-18 00:00:57 +000019#define CARDBUS_IO_SIZE 4096
20#define CARDBUS_MEM_SIZE (32 * 1024 * 1024)
Yinghai Lu304f24c2005-07-08 02:56:47 +000021
Elyes HAOUASe18cbea2018-05-02 21:20:59 +020022static void cardbus_record_bridge_resource(struct device *dev, resource_t moving,
Uwe Hermannd453dd02010-10-18 00:00:57 +000023 resource_t min_size, unsigned int index, unsigned long type)
Yinghai Lu304f24c2005-07-08 02:56:47 +000024{
Yinghai Lu304f24c2005-07-08 02:56:47 +000025 struct resource *resource;
Uwe Hermanne4870472010-11-04 23:23:47 +000026 unsigned long gran;
27 resource_t step;
Uwe Hermannd453dd02010-10-18 00:00:57 +000028
29 /* Initialize the constraints on the current bus. */
Myles Watson03adcfd2010-06-07 16:51:11 +000030 resource = NULL;
Uwe Hermanne4870472010-11-04 23:23:47 +000031 if (!moving)
32 return;
Uwe Hermannd453dd02010-10-18 00:00:57 +000033
Uwe Hermanne4870472010-11-04 23:23:47 +000034 resource = new_resource(dev, index);
35 resource->size = 0;
36 gran = 0;
37 step = 1;
38 while ((moving & step) == 0) {
39 gran += 1;
40 step <<= 1;
Yinghai Lu304f24c2005-07-08 02:56:47 +000041 }
Uwe Hermanne4870472010-11-04 23:23:47 +000042 resource->gran = gran;
43 resource->align = gran;
44 resource->limit = moving | (step - 1);
45 resource->flags = type;
46
47 /* Don't let the minimum size exceed what we can put in the resource. */
48 if ((min_size - 1) > resource->limit)
49 min_size = resource->limit + 1;
50
51 resource->size = min_size;
Yinghai Lu304f24c2005-07-08 02:56:47 +000052}
53
Elyes HAOUASe18cbea2018-05-02 21:20:59 +020054void cardbus_read_resources(struct device *dev)
Yinghai Lu304f24c2005-07-08 02:56:47 +000055{
56 resource_t moving_base, moving_limit, moving;
57 unsigned long type;
Uwe Hermannd453dd02010-10-18 00:00:57 +000058 u16 ctl;
Ronald G. Minnich43225bc2005-11-22 00:07:02 +000059
Uwe Hermannd453dd02010-10-18 00:00:57 +000060 /* See if needs a card control registers base address. */
Ronald G. Minnich43225bc2005-11-22 00:07:02 +000061
62 pci_get_resource(dev, PCI_BASE_ADDRESS_0);
63
64 compact_resources(dev);
65
Uwe Hermannd453dd02010-10-18 00:00:57 +000066 /* See which bridge I/O resources are implemented. */
67 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
Yinghai Lu304f24c2005-07-08 02:56:47 +000068 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
69 moving = moving_base & moving_limit;
70
Uwe Hermannd453dd02010-10-18 00:00:57 +000071 /* Initialize the I/O space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +000072 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +000073 PCI_CB_IO_BASE_0, IORESOURCE_IO);
Yinghai Lu304f24c2005-07-08 02:56:47 +000074
Uwe Hermannd453dd02010-10-18 00:00:57 +000075 /* See which bridge I/O resources are implemented. */
76 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
Yinghai Lu304f24c2005-07-08 02:56:47 +000077 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
78 moving = moving_base & moving_limit;
79
Uwe Hermannd453dd02010-10-18 00:00:57 +000080 /* Initialize the I/O space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +000081 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +000082 PCI_CB_IO_BASE_1, IORESOURCE_IO);
Yinghai Lu304f24c2005-07-08 02:56:47 +000083
Uwe Hermannd453dd02010-10-18 00:00:57 +000084 /* If I can, enable prefetch for mem0. */
Yinghai Lu304f24c2005-07-08 02:56:47 +000085 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
86 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
87 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
88 ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
89 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
90 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
91
Uwe Hermannd453dd02010-10-18 00:00:57 +000092 /* See which bridge memory resources are implemented. */
93 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
Yinghai Lu304f24c2005-07-08 02:56:47 +000094 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
95 moving = moving_base & moving_limit;
96
Uwe Hermannd453dd02010-10-18 00:00:57 +000097 /* Initialize the memory space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +000098 type = IORESOURCE_MEM;
Uwe Hermannd453dd02010-10-18 00:00:57 +000099 if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)
Yinghai Lu304f24c2005-07-08 02:56:47 +0000100 type |= IORESOURCE_PREFETCH;
Yinghai Lu304f24c2005-07-08 02:56:47 +0000101 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000102 PCI_CB_MEMORY_BASE_0, type);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000103
Uwe Hermannd453dd02010-10-18 00:00:57 +0000104 /* See which bridge memory resources are implemented. */
105 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000106 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
107 moving = moving_base & moving_limit;
108
Uwe Hermannd453dd02010-10-18 00:00:57 +0000109 /* Initialize the memory space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000110 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000111 PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000112
113 compact_resources(dev);
114}
115
Elyes HAOUASe18cbea2018-05-02 21:20:59 +0200116void cardbus_enable_resources(struct device *dev)
Yinghai Lu304f24c2005-07-08 02:56:47 +0000117{
Uwe Hermannd453dd02010-10-18 00:00:57 +0000118 u16 ctrl;
119
Yinghai Lu304f24c2005-07-08 02:56:47 +0000120 ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
Myles Watson894a3472010-06-09 22:41:35 +0000121 ctrl |= (dev->link_list->bridge_ctrl & (
Yinghai Lu304f24c2005-07-08 02:56:47 +0000122 PCI_BRIDGE_CTL_VGA |
123 PCI_BRIDGE_CTL_MASTER_ABORT |
124 PCI_BRIDGE_CTL_BUS_RESET));
Uwe Hermannd453dd02010-10-18 00:00:57 +0000125 /* Error check */
Kyösti Mälkki382e2162019-09-21 16:19:32 +0300126 ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000127 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
Kyösti Mälkki0bca0502019-09-21 16:21:47 +0300128 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000129
130 pci_dev_enable_resources(dev);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000131}
132
Yinghai Lu304f24c2005-07-08 02:56:47 +0000133struct device_operations default_cardbus_ops_bus = {
134 .read_resources = cardbus_read_resources,
135 .set_resources = pci_dev_set_resources,
136 .enable_resources = cardbus_enable_resources,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000137 .scan_bus = pci_scan_bridge,
Yinghai Lu304f24c2005-07-08 02:56:47 +0000138 .reset_bus = pci_bus_reset,
139};