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Patrick Georgi11f00792020-03-04 15:10:45 +01001/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin6b0cebc2016-09-16 16:15:14 -05002
Kyösti Mälkkia963acd2019-08-16 20:34:25 +03003#include <arch/romstage.h>
Aaron Durbin1e9a9142016-09-16 16:23:21 -05004#include <cbmem.h>
Aaron Durbin6b0cebc2016-09-16 16:15:14 -05005#include <console/console.h>
Nico Huberd67edca2018-11-13 19:28:07 +01006#include <cpu/x86/mtrr.h>
Aaron Durbin6b0cebc2016-09-16 16:15:14 -05007#include <main_decl.h>
8#include <program_loading.h>
Subrata Banik4f42eea2019-03-05 16:45:14 +05309#include <timestamp.h>
Marshall Dawsona102a022017-08-10 15:17:26 -060010
11/*
12 * Systems without a native coreboot cache-as-ram teardown may implement
13 * this to use an alternate method.
14 */
Aaron Durbin64031672018-04-21 14:45:32 -060015__weak void late_car_teardown(void) { /* do nothing */ }
Aaron Durbin6b0cebc2016-09-16 16:15:14 -050016
17void main(void)
18{
Marshall Dawsona102a022017-08-10 15:17:26 -060019 late_car_teardown();
Brenton Dong0a5971c2016-10-18 11:35:15 -070020
Aaron Durbin6b0cebc2016-09-16 16:15:14 -050021 console_init();
22
Kyösti Mälkki8b936892019-09-12 13:45:15 +030023 /*
24 * CBMEM needs to be recovered because timestamps rely on
25 * the cbmem infrastructure being around. Explicitly recover it.
26 */
Aaron Durbin1e9a9142016-09-16 16:23:21 -050027 cbmem_initialize();
28
Subrata Banik4f42eea2019-03-05 16:45:14 +053029 timestamp_add_now(TS_START_POSTCAR);
30
Nico Huberd67edca2018-11-13 19:28:07 +010031 display_mtrrs();
Aaron Durbin6b0cebc2016-09-16 16:15:14 -050032
33 /* Load and run ramstage. */
34 run_ramstage();
35}