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review.coreboot.org / coreboot / ae05d095b36ac835a6b1a221e6858065e5486888 / . / src / vendorcode / amd / agesa / f14 / Config / PlatformInstall.h
blob: 1a32ef3117f041eaac24588a0af80f552b8c399f [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]14 * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]21 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]31 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]32 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]43 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]54VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
55 //ModuleHeaderSignature
56 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]57 Int32FromChar ('0', '0', '0', '0'),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]58 //ModuleIdentifier[8]
59 AGESA_ID,
60 //ModuleVersion[12]
61 AGESA_VERSION_STRING,
62 //ModuleDispatcher
63 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
64 //NextBlock
65 NULL
66};
67
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]68/* Process solution defined socket / family installations
69 *
70 * As part of the release package for each image, define the options below to select the
71 * AGESA processor support included in that image.
72 */
73
74/* Default sockets to off */
75#define OPTION_G34_SOCKET_SUPPORT FALSE
76#define OPTION_C32_SOCKET_SUPPORT FALSE
77#define OPTION_S1G3_SOCKET_SUPPORT FALSE
78#define OPTION_S1G4_SOCKET_SUPPORT FALSE
79#define OPTION_ASB2_SOCKET_SUPPORT FALSE
80#define OPTION_FS1_SOCKET_SUPPORT FALSE
81#define OPTION_FM1_SOCKET_SUPPORT FALSE
82#define OPTION_FP1_SOCKET_SUPPORT FALSE
83#define OPTION_FT1_SOCKET_SUPPORT FALSE
84#define OPTION_AM3_SOCKET_SUPPORT FALSE
85
86/* Default families to off */
87#define OPTION_FAMILY10H FALSE
88#define OPTION_FAMILY12H FALSE
89#define OPTION_FAMILY14H FALSE
90#define OPTION_FAMILY15H FALSE
91
92
93/* Enable the appropriate socket support */
94#ifdef INSTALL_G34_SOCKET_SUPPORT
95 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
96 #undef OPTION_G34_SOCKET_SUPPORT
97 #define OPTION_G34_SOCKET_SUPPORT TRUE
98 #endif
99#endif
100
101#ifdef INSTALL_C32_SOCKET_SUPPORT
102 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
103 #undef OPTION_C32_SOCKET_SUPPORT
104 #define OPTION_C32_SOCKET_SUPPORT TRUE
105 #endif
106#endif
107
108#ifdef INSTALL_S1G3_SOCKET_SUPPORT
109 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
110 #undef OPTION_S1G3_SOCKET_SUPPORT
111 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
112 #endif
113#endif
114
115#ifdef INSTALL_S1G4_SOCKET_SUPPORT
116 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
117 #undef OPTION_S1G4_SOCKET_SUPPORT
118 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
119 #endif
120#endif
121
122#ifdef INSTALL_ASB2_SOCKET_SUPPORT
123 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
124 #undef OPTION_ASB2_SOCKET_SUPPORT
125 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
126 #endif
127#endif
128
129#ifdef INSTALL_FS1_SOCKET_SUPPORT
130 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
131 #undef OPTION_FS1_SOCKET_SUPPORT
132 #define OPTION_FS1_SOCKET_SUPPORT TRUE
133 #endif
134#endif
135
136#ifdef INSTALL_FM1_SOCKET_SUPPORT
137 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
138 #undef OPTION_FM1_SOCKET_SUPPORT
139 #define OPTION_FM1_SOCKET_SUPPORT TRUE
140 #endif
141#endif
142
143#ifdef INSTALL_FP1_SOCKET_SUPPORT
144 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
145 #undef OPTION_FP1_SOCKET_SUPPORT
146 #define OPTION_FP1_SOCKET_SUPPORT TRUE
147 #endif
148#endif
149
150#ifdef INSTALL_FT1_SOCKET_SUPPORT
151 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
152 #undef OPTION_FT1_SOCKET_SUPPORT
153 #define OPTION_FT1_SOCKET_SUPPORT TRUE
154 #endif
155#endif
156
157#ifdef INSTALL_AM3_SOCKET_SUPPORT
158 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
159 #undef OPTION_AM3_SOCKET_SUPPORT
160 #define OPTION_AM3_SOCKET_SUPPORT TRUE
161 #endif
162#endif
163
164
165/* Enable the appropriate family support */
166// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
167#ifdef INSTALL_FAMILY_10_SUPPORT
168 #if INSTALL_FAMILY_10_SUPPORT == TRUE
169 #undef OPTION_FAMILY10H
170 #define OPTION_FAMILY10H TRUE
171 #endif
172#endif
173
174// F12 is supported in FP1, FS1, & FM1
175#ifdef INSTALL_FAMILY_12_SUPPORT
176 #if INSTALL_FAMILY_12_SUPPORT == TRUE
177 #undef OPTION_FAMILY12H
178 #define OPTION_FAMILY12H TRUE
179 #endif
180#endif
181
182// F14 is supported in FT1
183#ifdef INSTALL_FAMILY_14_SUPPORT
184 #if INSTALL_FAMILY_14_SUPPORT == TRUE
185 #undef OPTION_FAMILY14H
186 #define OPTION_FAMILY14H TRUE
187 #endif
188#endif
189
190// F15 is supported in G34, C32, & AM3
191#ifdef INSTALL_FAMILY_15_SUPPORT
192 #if INSTALL_FAMILY_15_SUPPORT == TRUE
193 #undef OPTION_FAMILY15H
194 #define OPTION_FAMILY15H TRUE
195 #endif
196#endif
197
198
199/* Turn off families not required by socket designations */
200#if (OPTION_FAMILY10H == TRUE)
201 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
202 #undef OPTION_FAMILY10H
203 #define OPTION_FAMILY10H FALSE
204 #endif
205#endif
206
207#if (OPTION_FAMILY12H == TRUE)
208 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
209 #undef OPTION_FAMILY12H
210 #define OPTION_FAMILY12H FALSE
211 #endif
212#endif
213
214#if (OPTION_FAMILY14H == TRUE)
215 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
216 #undef OPTION_FAMILY14H
217 #define OPTION_FAMILY14H FALSE
218 #endif
219#endif
220
221#if (OPTION_FAMILY15H == TRUE)
222 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
223 #undef OPTION_FAMILY15H
224 #define OPTION_FAMILY15H FALSE
225 #endif
226#endif
227
228
229/* Check for invalid combinations of socket/family */
230#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
231 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
232 #error No G34 supported families included in the build
233 #endif
234#endif
235
236#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
237 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
238 #error No C32 supported families included in the build
239 #endif
240#endif
241
242#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
243 #if (OPTION_FAMILY10H == FALSE)
244 #error No S1G3 supported families included in the build
245 #endif
246#endif
247
248#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
249 #if (OPTION_FAMILY10H == FALSE)
250 #error No S1G4 supported families included in the build
251 #endif
252#endif
253
254#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
255 #if (OPTION_FAMILY10H == FALSE)
256 #error No ASB2 supported families included in the build
257 #endif
258#endif
259
260#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
261 #if (OPTION_FAMILY12H == FALSE)
262 #error No FS1 supported families included in the build
263 #endif
264#endif
265
266#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
267 #if (OPTION_FAMILY12H == FALSE)
268 #error No FM1 supported families included in the build
269 #endif
270#endif
271
272#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
273 #if (OPTION_FAMILY12H == FALSE)
274 #error No FP1 supported families included in the build
275 #endif
276#endif
277
278#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
279 #if (OPTION_FAMILY14H == FALSE)
280 #error No FT1 supported families included in the build
281 #endif
282#endif
283
284#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
285 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
286 #error No AM3 supported families included in the build
287 #endif
288#endif
289
290
291/* Process AGESA private data
292 *
293 * Turn on appropriate CPU models and memory controllers,
294 * as well as some other memory controls.
295 */
296
297/* Default all models to off */
298#define OPTION_FAMILY10H_BL FALSE
299#define OPTION_FAMILY10H_DA FALSE
300#define OPTION_FAMILY10H_HY FALSE
301#define OPTION_FAMILY10H_PH FALSE
302#define OPTION_FAMILY10H_RB FALSE
303#define OPTION_FAMILY12H_LN FALSE
304#define OPTION_FAMILY14H_ON FALSE
305#define OPTION_FAMILY15H_OR FALSE
306
307/* Default all memory controllers to off */
308#define OPTION_MEMCTLR_DR FALSE
309#define OPTION_MEMCTLR_HY FALSE
310#define OPTION_MEMCTLR_OR FALSE
311#define OPTION_MEMCTLR_C32 FALSE
312#define OPTION_MEMCTLR_DA FALSE
313#define OPTION_MEMCTLR_LN FALSE
314#define OPTION_MEMCTLR_ON FALSE
315#define OPTION_MEMCTLR_Ni FALSE
316#define OPTION_MEMCTLR_PH FALSE
317#define OPTION_MEMCTLR_RB FALSE
318
319/* Default all memory controls to off */
320#define OPTION_HW_WRITE_LEV_TRAINING FALSE
321#define OPTION_SW_WRITE_LEV_TRAINING FALSE
322#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
323#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
324#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
325#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
326#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
327#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
328#define OPTION_MAX_RD_LAT_TRAINING FALSE
329#define OPTION_HW_DRAM_INIT FALSE
330#define OPTION_SW_DRAM_INIT FALSE
331#define OPTION_S3_MEM_SUPPORT FALSE
332#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
333
334/* Defaults for public user options */
335#define OPTION_UDIMMS FALSE
336#define OPTION_RDIMMS FALSE
337#define OPTION_SODIMMS FALSE
338#define OPTION_LRDIMMS FALSE
339#define OPTION_DDR2 FALSE
340#define OPTION_DDR3 FALSE
341#define OPTION_ECC FALSE
342#define OPTION_BANK_INTERLEAVE FALSE
343#define OPTION_DCT_INTERLEAVE FALSE
344#define OPTION_NODE_INTERLEAVE FALSE
345#define OPTION_PARALLEL_TRAINING FALSE
346#define OPTION_ONLINE_SPARE FALSE
347#define OPTION_MEM_RESTORE FALSE
348#define OPTION_DIMM_EXCLUDE FALSE
349
350/* Default all CPU controls to off */
351#define OPTION_MULTISOCKET FALSE
352#define OPTION_SRAT FALSE
353#define OPTION_SLIT FALSE
354#define OPTION_HT_ASSIST FALSE
355#define OPTION_ATM_MODE FALSE
356#define OPTION_CPU_CORELEVLING FALSE
357#define OPTION_MSG_BASED_C1E FALSE
358#define OPTION_CPU_CFOH FALSE
359#define OPTION_C6_STATE FALSE
360#define OPTION_IO_CSTATE FALSE
361#define OPTION_CPB FALSE
362#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
363#define OPTION_S3SCRIPT FALSE
364#define OPTION_GFX_RECOVERY FALSE
365
366/* Enable all private controls based on socket/family enables */
367#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
368 #if (OPTION_FAMILY10H == TRUE)
369 #undef OPTION_FAMILY10H_HY
370 #define OPTION_FAMILY10H_HY TRUE
371 #undef OPTION_MEMCTLR_HY
372 #define OPTION_MEMCTLR_HY TRUE
373 #undef OPTION_HW_WRITE_LEV_TRAINING
374 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
375 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
376 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
377 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
378 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
379 #undef OPTION_MAX_RD_LAT_TRAINING
380 #define OPTION_MAX_RD_LAT_TRAINING TRUE
381 #undef OPTION_SW_DRAM_INIT
382 #define OPTION_SW_DRAM_INIT TRUE
383 #undef OPTION_S3_MEM_SUPPORT
384 #define OPTION_S3_MEM_SUPPORT TRUE
385 #undef OPTION_MULTISOCKET
386 #define OPTION_MULTISOCKET TRUE
387 #undef OPTION_SRAT
388 #define OPTION_SRAT TRUE
389 #undef OPTION_SLIT
390 #define OPTION_SLIT TRUE
391 #undef OPTION_HT_ASSIST
392 #define OPTION_HT_ASSIST TRUE
393 #undef OPTION_CPU_CORELEVLING
394 #define OPTION_CPU_CORELEVLING TRUE
395 #undef OPTION_MSG_BASED_C1E
396 #define OPTION_MSG_BASED_C1E TRUE
397 #undef OPTION_CPU_CFOH
398 #define OPTION_CPU_CFOH TRUE
399 #undef OPTION_UDIMMS
400 #define OPTION_UDIMMS TRUE
401 #undef OPTION_RDIMMS
402 #define OPTION_RDIMMS TRUE
403 #undef OPTION_SODIMMS
404 #define OPTION_SODIMMS TRUE
405 #undef OPTION_DDR3
406 #define OPTION_DDR3 TRUE
407 #undef OPTION_ECC
408 #define OPTION_ECC TRUE
409 #undef OPTION_BANK_INTERLEAVE
410 #define OPTION_BANK_INTERLEAVE TRUE
411 #undef OPTION_DCT_INTERLEAVE
412 #define OPTION_DCT_INTERLEAVE TRUE
413 #undef OPTION_NODE_INTERLEAVE
414 #define OPTION_NODE_INTERLEAVE TRUE
415 #undef OPTION_PARALLEL_TRAINING
416 #define OPTION_PARALLEL_TRAINING TRUE
417 #undef OPTION_MEM_RESTORE
418 #define OPTION_MEM_RESTORE TRUE
419 #undef OPTION_ONLINE_SPARE
420 #define OPTION_ONLINE_SPARE TRUE
421 #undef OPTION_DIMM_EXCLUDE
422 #define OPTION_DIMM_EXCLUDE TRUE
423 #endif
424 #if (OPTION_FAMILY15H == TRUE)
425 #undef OPTION_FAMILY15H_OR
426 #define OPTION_FAMILY15H_OR TRUE
427 #undef OPTION_MEMCTLR_OR
428 #define OPTION_MEMCTLR_OR TRUE
429 #undef OPTION_HW_WRITE_LEV_TRAINING
430 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
431 #undef OPTION_CONTINOUS_PATTERN_GENERATION
432 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
433 #undef OPTION_HW_DQS_REC_EN_TRAINING
434 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
435 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
436 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
437 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
438 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
439 #undef OPTION_MAX_RD_LAT_TRAINING
440 #define OPTION_MAX_RD_LAT_TRAINING TRUE
441 #undef OPTION_SW_DRAM_INIT
442 #define OPTION_SW_DRAM_INIT TRUE
443 #undef OPTION_S3_MEM_SUPPORT
444 #define OPTION_S3_MEM_SUPPORT TRUE
445 #undef OPTION_MULTISOCKET
446 #define OPTION_MULTISOCKET TRUE
447 #undef OPTION_C6_STATE
448 #define OPTION_C6_STATE TRUE
449 #undef OPTION_IO_CSTATE
450 #define OPTION_IO_CSTATE TRUE
451 #undef OPTION_CPB
452 #define OPTION_CPB TRUE
453 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
454 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
455 #undef OPTION_SRAT
456 #define OPTION_SRAT TRUE
457 #undef OPTION_SLIT
458 #define OPTION_SLIT TRUE
459 #undef OPTION_HT_ASSIST
460 #define OPTION_HT_ASSIST TRUE
461 #undef OPTION_ATM_MODE
462 #define OPTION_ATM_MODE TRUE
463 #undef OPTION_CPU_CORELEVLING
464 #define OPTION_CPU_CORELEVLING TRUE
465 #undef OPTION_MSG_BASED_C1E
466 #define OPTION_MSG_BASED_C1E TRUE
467 #undef OPTION_CPU_CFOH
468 #define OPTION_CPU_CFOH TRUE
469 #undef OPTION_UDIMMS
470 #define OPTION_UDIMMS TRUE
471 #undef OPTION_RDIMMS
472 #define OPTION_RDIMMS TRUE
473 #undef OPTION_SODIMMS
474 #define OPTION_SODIMMS TRUE
475 #undef OPTION_LRDIMMS
476 #define OPTION_LRDIMMS TRUE
477 #undef OPTION_DDR3
478 #define OPTION_DDR3 TRUE
479 #undef OPTION_ECC
480 #define OPTION_ECC TRUE
481 #undef OPTION_BANK_INTERLEAVE
482 #define OPTION_BANK_INTERLEAVE TRUE
483 #undef OPTION_DCT_INTERLEAVE
484 #define OPTION_DCT_INTERLEAVE TRUE
485 #undef OPTION_NODE_INTERLEAVE
486 #define OPTION_NODE_INTERLEAVE TRUE
487 #undef OPTION_MEM_RESTORE
488 #define OPTION_MEM_RESTORE TRUE
489 #undef OPTION_ONLINE_SPARE
490 #define OPTION_ONLINE_SPARE TRUE
491 #undef OPTION_DIMM_EXCLUDE
492 #define OPTION_DIMM_EXCLUDE TRUE
493 #endif
494#endif
495
496#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
497 #if (OPTION_FAMILY10H == TRUE)
498 #undef OPTION_FAMILY10H_HY
499 #define OPTION_FAMILY10H_HY TRUE
500 #undef OPTION_MEMCTLR_C32
501 #define OPTION_MEMCTLR_C32 TRUE
502 #undef OPTION_HW_WRITE_LEV_TRAINING
503 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
504 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
505 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
506 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
507 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
508 #undef OPTION_MAX_RD_LAT_TRAINING
509 #define OPTION_MAX_RD_LAT_TRAINING TRUE
510 #undef OPTION_SW_DRAM_INIT
511 #define OPTION_SW_DRAM_INIT TRUE
512 #undef OPTION_S3_MEM_SUPPORT
513 #define OPTION_S3_MEM_SUPPORT TRUE
514 #undef OPTION_ADDR_TO_CS_TRANSLATOR
515 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
516 #undef OPTION_MULTISOCKET
517 #define OPTION_MULTISOCKET TRUE
518 #undef OPTION_SRAT
519 #define OPTION_SRAT TRUE
520 #undef OPTION_SLIT
521 #define OPTION_SLIT TRUE
522 #undef OPTION_HT_ASSIST
523 #define OPTION_HT_ASSIST TRUE
524 #undef OPTION_CPU_CORELEVLING
525 #define OPTION_CPU_CORELEVLING TRUE
526 #undef OPTION_MSG_BASED_C1E
527 #define OPTION_MSG_BASED_C1E TRUE
528 #undef OPTION_CPU_CFOH
529 #define OPTION_CPU_CFOH TRUE
530 #undef OPTION_UDIMMS
531 #define OPTION_UDIMMS TRUE
532 #undef OPTION_RDIMMS
533 #define OPTION_RDIMMS TRUE
534 #undef OPTION_SODIMMS
535 #define OPTION_SODIMMS TRUE
536 #undef OPTION_DDR3
537 #define OPTION_DDR3 TRUE
538 #undef OPTION_ECC
539 #define OPTION_ECC TRUE
540 #undef OPTION_BANK_INTERLEAVE
541 #define OPTION_BANK_INTERLEAVE TRUE
542 #undef OPTION_DCT_INTERLEAVE
543 #define OPTION_DCT_INTERLEAVE TRUE
544 #undef OPTION_NODE_INTERLEAVE
545 #define OPTION_NODE_INTERLEAVE TRUE
546 #undef OPTION_PARALLEL_TRAINING
547 #define OPTION_PARALLEL_TRAINING TRUE
548 #undef OPTION_MEM_RESTORE
549 #define OPTION_MEM_RESTORE TRUE
550 #undef OPTION_ONLINE_SPARE
551 #define OPTION_ONLINE_SPARE TRUE
552 #undef OPTION_DIMM_EXCLUDE
553 #define OPTION_DIMM_EXCLUDE TRUE
554 #endif
555 #if (OPTION_FAMILY15H == TRUE)
556 #undef OPTION_FAMILY15H_OR
557 #define OPTION_FAMILY15H_OR TRUE
558 #undef OPTION_MEMCTLR_OR
559 #define OPTION_MEMCTLR_OR TRUE
560 #undef OPTION_HW_WRITE_LEV_TRAINING
561 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
562 #undef OPTION_CONTINOUS_PATTERN_GENERATION
563 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
564 #undef OPTION_HW_DQS_REC_EN_TRAINING
565 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
566 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
567 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
568 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
569 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
570 #undef OPTION_MAX_RD_LAT_TRAINING
571 #define OPTION_MAX_RD_LAT_TRAINING TRUE
572 #undef OPTION_SW_DRAM_INIT
573 #define OPTION_SW_DRAM_INIT TRUE
574 #undef OPTION_S3_MEM_SUPPORT
575 #define OPTION_S3_MEM_SUPPORT TRUE
576 #undef OPTION_ADDR_TO_CS_TRANSLATOR
577 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
578 #undef OPTION_MULTISOCKET
579 #define OPTION_MULTISOCKET TRUE
580 #undef OPTION_C6_STATE
581 #define OPTION_C6_STATE TRUE
582 #undef OPTION_IO_CSTATE
583 #define OPTION_IO_CSTATE TRUE
584 #undef OPTION_CPB
585 #define OPTION_CPB TRUE
586 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
587 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
588 #undef OPTION_SRAT
589 #define OPTION_SRAT TRUE
590 #undef OPTION_SLIT
591 #define OPTION_SLIT TRUE
592 #undef OPTION_HT_ASSIST
593 #define OPTION_HT_ASSIST TRUE
594 #undef OPTION_ATM_MODE
595 #define OPTION_ATM_MODE TRUE
596 #undef OPTION_CPU_CORELEVLING
597 #define OPTION_CPU_CORELEVLING TRUE
598 #undef OPTION_MSG_BASED_C1E
599 #define OPTION_MSG_BASED_C1E TRUE
600 #undef OPTION_CPU_CFOH
601 #define OPTION_CPU_CFOH TRUE
602 #undef OPTION_UDIMMS
603 #define OPTION_UDIMMS TRUE
604 #undef OPTION_RDIMMS
605 #define OPTION_RDIMMS TRUE
606 #undef OPTION_SODIMMS
607 #define OPTION_SODIMMS TRUE
608 #undef OPTION_LRDIMMS
609 #define OPTION_LRDIMMS TRUE
610 #undef OPTION_DDR3
611 #define OPTION_DDR3 TRUE
612 #undef OPTION_ECC
613 #define OPTION_ECC TRUE
614 #undef OPTION_BANK_INTERLEAVE
615 #define OPTION_BANK_INTERLEAVE TRUE
616 #undef OPTION_DCT_INTERLEAVE
617 #define OPTION_DCT_INTERLEAVE TRUE
618 #undef OPTION_NODE_INTERLEAVE
619 #define OPTION_NODE_INTERLEAVE TRUE
620 #undef OPTION_MEM_RESTORE
621 #define OPTION_MEM_RESTORE TRUE
622 #undef OPTION_ONLINE_SPARE
623 #define OPTION_ONLINE_SPARE TRUE
624 #undef OPTION_DIMM_EXCLUDE
625 #define OPTION_DIMM_EXCLUDE TRUE
626 #endif
627#endif
628
629#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
630 #if (OPTION_FAMILY10H == TRUE)
631 #undef OPTION_FAMILY10H_BL
632 #define OPTION_FAMILY10H_BL TRUE
633 #undef OPTION_FAMILY10H_DA
634 #define OPTION_FAMILY10H_DA TRUE
635 #undef OPTION_MEMCTLR_DA
636 #define OPTION_MEMCTLR_DA TRUE
637 #undef OPTION_HW_WRITE_LEV_TRAINING
638 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
639 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
640 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
641 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
642 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
643 #undef OPTION_MAX_RD_LAT_TRAINING
644 #define OPTION_MAX_RD_LAT_TRAINING TRUE
645 #undef OPTION_SW_DRAM_INIT
646 #define OPTION_SW_DRAM_INIT TRUE
647 #undef OPTION_S3_MEM_SUPPORT
648 #define OPTION_S3_MEM_SUPPORT TRUE
649 #undef OPTION_CPU_CORELEVLING
650 #define OPTION_CPU_CORELEVLING TRUE
651 #undef OPTION_CPU_CFOH
652 #define OPTION_CPU_CFOH TRUE
653 #undef OPTION_UDIMMS
654 #define OPTION_UDIMMS TRUE
655 #undef OPTION_SODIMMS
656 #define OPTION_SODIMMS TRUE
657 #undef OPTION_DDR3
658 #define OPTION_DDR3 TRUE
659 #undef OPTION_ECC
660 #define OPTION_ECC TRUE
661 #undef OPTION_BANK_INTERLEAVE
662 #define OPTION_BANK_INTERLEAVE TRUE
663 #undef OPTION_DCT_INTERLEAVE
664 #define OPTION_DCT_INTERLEAVE TRUE
665 #undef OPTION_NODE_INTERLEAVE
666 #define OPTION_NODE_INTERLEAVE TRUE
667 #undef OPTION_PARALLEL_TRAINING
668 #define OPTION_PARALLEL_TRAINING TRUE
669 #undef OPTION_MEM_RESTORE
670 #define OPTION_MEM_RESTORE TRUE
671 #undef OPTION_ONLINE_SPARE
672 #define OPTION_ONLINE_SPARE TRUE
673 #undef OPTION_DIMM_EXCLUDE
674 #define OPTION_DIMM_EXCLUDE TRUE
675 #endif
676#endif
677
678#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
679 #if (OPTION_FAMILY10H == TRUE)
680 #undef OPTION_FAMILY10H_BL
681 #define OPTION_FAMILY10H_BL TRUE
682 #undef OPTION_FAMILY10H_DA
683 #define OPTION_FAMILY10H_DA TRUE
684 #undef OPTION_MEMCTLR_DA
685 #define OPTION_MEMCTLR_DA TRUE
686 #undef OPTION_HW_WRITE_LEV_TRAINING
687 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
688 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
689 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
690 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
691 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
692 #undef OPTION_MAX_RD_LAT_TRAINING
693 #define OPTION_MAX_RD_LAT_TRAINING TRUE
694 #undef OPTION_SW_DRAM_INIT
695 #define OPTION_SW_DRAM_INIT TRUE
696 #undef OPTION_S3_MEM_SUPPORT
697 #define OPTION_S3_MEM_SUPPORT TRUE
698 #undef OPTION_CPU_CORELEVLING
699 #define OPTION_CPU_CORELEVLING TRUE
700 #undef OPTION_CPU_CFOH
701 #define OPTION_CPU_CFOH TRUE
702 #undef OPTION_UDIMMS
703 #define OPTION_UDIMMS TRUE
704 #undef OPTION_SODIMMS
705 #define OPTION_SODIMMS TRUE
706 #undef OPTION_DDR3
707 #define OPTION_DDR3 TRUE
708 #undef OPTION_ECC
709 #define OPTION_ECC TRUE
710 #undef OPTION_BANK_INTERLEAVE
711 #define OPTION_BANK_INTERLEAVE TRUE
712 #undef OPTION_DCT_INTERLEAVE
713 #define OPTION_DCT_INTERLEAVE TRUE
714 #undef OPTION_NODE_INTERLEAVE
715 #define OPTION_NODE_INTERLEAVE TRUE
716 #undef OPTION_MEM_RESTORE
717 #define OPTION_MEM_RESTORE TRUE
718 #undef OPTION_DIMM_EXCLUDE
719 #define OPTION_DIMM_EXCLUDE TRUE
720 #endif
721#endif
722
723#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
724 #if (OPTION_FAMILY10H == TRUE)
725 #undef OPTION_FAMILY10H_BL
726 #define OPTION_FAMILY10H_BL TRUE
727 #undef OPTION_FAMILY10H_DA
728 #define OPTION_FAMILY10H_DA TRUE
729 #undef OPTION_MEMCTLR_Ni
730 #define OPTION_MEMCTLR_Ni TRUE
731 #undef OPTION_HW_WRITE_LEV_TRAINING
732 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
733 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
734 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
735 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
736 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
737 #undef OPTION_MAX_RD_LAT_TRAINING
738 #define OPTION_MAX_RD_LAT_TRAINING TRUE
739 #undef OPTION_SW_DRAM_INIT
740 #define OPTION_SW_DRAM_INIT TRUE
741 #undef OPTION_S3_MEM_SUPPORT
742 #define OPTION_S3_MEM_SUPPORT TRUE
743 #undef OPTION_CPU_CORELEVLING
744 #define OPTION_CPU_CORELEVLING TRUE
745 #undef OPTION_CPU_CFOH
746 #define OPTION_CPU_CFOH TRUE
747 #undef OPTION_UDIMMS
748 #define OPTION_UDIMMS TRUE
749 #undef OPTION_SODIMMS
750 #define OPTION_SODIMMS TRUE
751 #undef OPTION_DDR3
752 #define OPTION_DDR3 TRUE
753 #undef OPTION_ECC
754 #define OPTION_ECC TRUE
755 #undef OPTION_BANK_INTERLEAVE
756 #define OPTION_BANK_INTERLEAVE TRUE
757 #undef OPTION_DCT_INTERLEAVE
758 #define OPTION_DCT_INTERLEAVE TRUE
759 #undef OPTION_NODE_INTERLEAVE
760 #define OPTION_NODE_INTERLEAVE TRUE
761 #undef OPTION_MEM_RESTORE
762 #define OPTION_MEM_RESTORE TRUE
763 #undef OPTION_DIMM_EXCLUDE
764 #define OPTION_DIMM_EXCLUDE TRUE
765 #endif
766#endif
767
768#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
769 #if (OPTION_FAMILY12H == TRUE)
770 #undef OPTION_FAMILY12H_LN
771 #define OPTION_FAMILY12H_LN TRUE
772 #undef OPTION_MEMCTLR_LN
773 #define OPTION_MEMCTLR_LN TRUE
774 #undef OPTION_HW_WRITE_LEV_TRAINING
775 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
776 #undef OPTION_CONTINOUS_PATTERN_GENERATION
777 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
778 #undef OPTION_HW_DQS_REC_EN_TRAINING
779 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
780 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
781 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
782 #undef OPTION_MAX_RD_LAT_TRAINING
783 #define OPTION_MAX_RD_LAT_TRAINING TRUE
784 #undef OPTION_SW_DRAM_INIT
785 #define OPTION_SW_DRAM_INIT TRUE
786 #undef OPTION_S3_MEM_SUPPORT
787 #define OPTION_S3_MEM_SUPPORT TRUE
788 #undef OPTION_GFX_RECOVERY
789 #define OPTION_GFX_RECOVERY TRUE
790 #undef OPTION_C6_STATE
791 #define OPTION_C6_STATE TRUE
792 #undef OPTION_IO_CSTATE
793 #define OPTION_IO_CSTATE TRUE
794 #undef OPTION_CPB
795 #define OPTION_CPB TRUE
796 #undef OPTION_S3SCRIPT
797 #define OPTION_S3SCRIPT TRUE
798 #undef OPTION_UDIMMS
799 #define OPTION_UDIMMS TRUE
800 #undef OPTION_SODIMMS
801 #define OPTION_SODIMMS TRUE
802 #undef OPTION_DDR3
803 #define OPTION_DDR3 TRUE
804 #undef OPTION_BANK_INTERLEAVE
805 #define OPTION_BANK_INTERLEAVE TRUE
806 #undef OPTION_DCT_INTERLEAVE
807 #define OPTION_DCT_INTERLEAVE TRUE
808 #undef OPTION_MEM_RESTORE
809 #define OPTION_MEM_RESTORE TRUE
810 #undef OPTION_DIMM_EXCLUDE
811 #define OPTION_DIMM_EXCLUDE TRUE
812 #endif
813#endif
814
815#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
816 #if (OPTION_FAMILY12H == TRUE)
817 #undef OPTION_FAMILY12H_LN
818 #define OPTION_FAMILY12H_LN TRUE
819 #undef OPTION_MEMCTLR_LN
820 #define OPTION_MEMCTLR_LN TRUE
821 #undef OPTION_HW_WRITE_LEV_TRAINING
822 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
823 #undef OPTION_CONTINOUS_PATTERN_GENERATION
824 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
825 #undef OPTION_HW_DQS_REC_EN_TRAINING
826 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
827 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
828 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
829 #undef OPTION_MAX_RD_LAT_TRAINING
830 #define OPTION_MAX_RD_LAT_TRAINING TRUE
831 #undef OPTION_SW_DRAM_INIT
832 #define OPTION_SW_DRAM_INIT TRUE
833 #undef OPTION_S3_MEM_SUPPORT
834 #define OPTION_S3_MEM_SUPPORT TRUE
835 #undef OPTION_GFX_RECOVERY
836 #define OPTION_GFX_RECOVERY TRUE
837 #undef OPTION_C6_STATE
838 #define OPTION_C6_STATE TRUE
839 #undef OPTION_IO_CSTATE
840 #define OPTION_IO_CSTATE TRUE
841 #undef OPTION_CPB
842 #define OPTION_CPB TRUE
843 #undef OPTION_S3SCRIPT
844 #define OPTION_S3SCRIPT TRUE
845 #undef OPTION_UDIMMS
846 #define OPTION_UDIMMS TRUE
847 #undef OPTION_SODIMMS
848 #define OPTION_SODIMMS TRUE
849 #undef OPTION_DDR3
850 #define OPTION_DDR3 TRUE
851 #undef OPTION_BANK_INTERLEAVE
852 #define OPTION_BANK_INTERLEAVE TRUE
853 #undef OPTION_DCT_INTERLEAVE
854 #define OPTION_DCT_INTERLEAVE TRUE
855 #undef OPTION_MEM_RESTORE
856 #define OPTION_MEM_RESTORE TRUE
857 #undef OPTION_DIMM_EXCLUDE
858 #define OPTION_DIMM_EXCLUDE TRUE
859 #endif
860#endif
861
862#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
863 #if (OPTION_FAMILY12H == TRUE)
864 #undef OPTION_FAMILY12H_LN
865 #define OPTION_FAMILY12H_LN TRUE
866 #undef OPTION_MEMCTLR_LN
867 #define OPTION_MEMCTLR_LN TRUE
868 #undef OPTION_HW_WRITE_LEV_TRAINING
869 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
870 #undef OPTION_CONTINOUS_PATTERN_GENERATION
871 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
872 #undef OPTION_HW_DQS_REC_EN_TRAINING
873 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
874 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
875 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
876 #undef OPTION_MAX_RD_LAT_TRAINING
877 #define OPTION_MAX_RD_LAT_TRAINING TRUE
878 #undef OPTION_SW_DRAM_INIT
879 #define OPTION_SW_DRAM_INIT TRUE
880 #undef OPTION_S3_MEM_SUPPORT
881 #define OPTION_S3_MEM_SUPPORT TRUE
882 #undef OPTION_ADDR_TO_CS_TRANSLATOR
883 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
884 #undef OPTION_GFX_RECOVERY
885 #define OPTION_GFX_RECOVERY TRUE
886 #undef OPTION_C6_STATE
887 #define OPTION_C6_STATE TRUE
888 #undef OPTION_IO_CSTATE
889 #define OPTION_IO_CSTATE TRUE
890 #undef OPTION_CPB
891 #define OPTION_CPB TRUE
892 #undef OPTION_S3SCRIPT
893 #define OPTION_S3SCRIPT TRUE
894 #undef OPTION_UDIMMS
895 #define OPTION_UDIMMS TRUE
896 #undef OPTION_SODIMMS
897 #define OPTION_SODIMMS TRUE
898 #undef OPTION_DDR3
899 #define OPTION_DDR3 TRUE
900 #undef OPTION_BANK_INTERLEAVE
901 #define OPTION_BANK_INTERLEAVE TRUE
902 #undef OPTION_DCT_INTERLEAVE
903 #define OPTION_DCT_INTERLEAVE TRUE
904 #undef OPTION_MEM_RESTORE
905 #define OPTION_MEM_RESTORE TRUE
906 #undef OPTION_ONLINE_SPARE
907 #define OPTION_ONLINE_SPARE TRUE
908 #undef OPTION_DIMM_EXCLUDE
909 #define OPTION_DIMM_EXCLUDE TRUE
910 #endif
911#endif
912
913#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
914 #if (OPTION_FAMILY14H == TRUE)
915 #undef OPTION_FAMILY14H_ON
916 #define OPTION_FAMILY14H_ON TRUE
917 #undef OPTION_MEMCTLR_ON
918 #define OPTION_MEMCTLR_ON TRUE
919 #undef OPTION_HW_WRITE_LEV_TRAINING
920 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
921 #undef OPTION_CONTINOUS_PATTERN_GENERATION
922 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
923 #undef OPTION_MAX_RD_LAT_TRAINING
924 #define OPTION_MAX_RD_LAT_TRAINING TRUE
925 #undef OPTION_HW_DQS_REC_EN_TRAINING
926 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
927 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
928 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
929 #undef OPTION_SW_DRAM_INIT
930 #define OPTION_SW_DRAM_INIT TRUE
931 #undef OPTION_S3_MEM_SUPPORT
932 #define OPTION_S3_MEM_SUPPORT TRUE
933 #undef OPTION_GFX_RECOVERY
934 #define OPTION_GFX_RECOVERY TRUE
935 #undef OPTION_C6_STATE
936 #define OPTION_C6_STATE TRUE
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]937 #undef OPTION_CPB
938 #define OPTION_CPB TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]939 #undef OPTION_IO_CSTATE
940 #define OPTION_IO_CSTATE TRUE
941 #undef OPTION_S3SCRIPT
942 #define OPTION_S3SCRIPT TRUE
943 #undef OPTION_UDIMMS
944 #define OPTION_UDIMMS TRUE
945 #undef OPTION_SODIMMS
946 #define OPTION_SODIMMS TRUE
947 #undef OPTION_DDR3
948 #define OPTION_DDR3 TRUE
949 #undef OPTION_BANK_INTERLEAVE
950 #define OPTION_BANK_INTERLEAVE TRUE
951 #undef OPTION_MEM_RESTORE
952 #define OPTION_MEM_RESTORE TRUE
953 #undef OPTION_DIMM_EXCLUDE
954 #define OPTION_DIMM_EXCLUDE TRUE
955 #endif
956#endif
957
958#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
959 #if (OPTION_FAMILY10H == TRUE)
960 #undef OPTION_FAMILY10H_BL
961 #define OPTION_FAMILY10H_BL TRUE
962 #undef OPTION_FAMILY10H_DA
963 #define OPTION_FAMILY10H_DA TRUE
964 #undef OPTION_FAMILY10H_PH
965 #define OPTION_FAMILY10H_PH TRUE
966 #undef OPTION_FAMILY10H_RB
967 #define OPTION_FAMILY10H_RB TRUE
968 #undef OPTION_MEMCTLR_RB
969 #define OPTION_MEMCTLR_RB TRUE
970 #undef OPTION_MEMCTLR_DA
971 #define OPTION_MEMCTLR_DA TRUE
972 #undef OPTION_MEMCTLR_PH
973 #define OPTION_MEMCTLR_PH TRUE
974 #undef OPTION_HW_WRITE_LEV_TRAINING
975 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
976 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
977 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
978 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
979 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
980 #undef OPTION_MAX_RD_LAT_TRAINING
981 #define OPTION_MAX_RD_LAT_TRAINING TRUE
982 #undef OPTION_SW_DRAM_INIT
983 #define OPTION_SW_DRAM_INIT TRUE
984 #undef OPTION_S3_MEM_SUPPORT
985 #define OPTION_S3_MEM_SUPPORT TRUE
986 #undef OPTION_CPU_CORELEVLING
987 #define OPTION_CPU_CORELEVLING TRUE
988 #undef OPTION_CPU_CFOH
989 #define OPTION_CPU_CFOH TRUE
990 #undef OPTION_IO_CSTATE
991 #define OPTION_IO_CSTATE TRUE
992 #undef OPTION_CPB
993 #define OPTION_CPB TRUE
994 #undef OPTION_UDIMMS
995 #define OPTION_UDIMMS TRUE
996 #undef OPTION_SODIMMS
997 #define OPTION_SODIMMS TRUE
998 #undef OPTION_DDR3
999 #define OPTION_DDR3 TRUE
1000 #undef OPTION_ECC
1001 #define OPTION_ECC TRUE
1002 #undef OPTION_BANK_INTERLEAVE
1003 #define OPTION_BANK_INTERLEAVE TRUE
1004 #undef OPTION_DCT_INTERLEAVE
1005 #define OPTION_DCT_INTERLEAVE TRUE
1006 #undef OPTION_NODE_INTERLEAVE
1007 #define OPTION_NODE_INTERLEAVE TRUE
1008 #undef OPTION_PARALLEL_TRAINING
1009 #define OPTION_PARALLEL_TRAINING TRUE
1010 #undef OPTION_MEM_RESTORE
1011 #define OPTION_MEM_RESTORE TRUE
1012 #undef OPTION_ONLINE_SPARE
1013 #define OPTION_ONLINE_SPARE TRUE
1014 #undef OPTION_DIMM_EXCLUDE
1015 #define OPTION_DIMM_EXCLUDE TRUE
1016 #endif
1017 #if (OPTION_FAMILY15H == TRUE)
1018 #undef OPTION_FAMILY15H_OR
1019 #define OPTION_FAMILY15H_OR TRUE
1020 #undef OPTION_MEMCTLR_OR
1021 #define OPTION_MEMCTLR_OR TRUE
1022 #undef OPTION_HW_WRITE_LEV_TRAINING
1023 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1024 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1025 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1026 #undef OPTION_HW_DQS_REC_EN_TRAINING
1027 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1028 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1029 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1030 #undef OPTION_MAX_RD_LAT_TRAINING
1031 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1032 #undef OPTION_SW_DRAM_INIT
1033 #define OPTION_SW_DRAM_INIT TRUE
1034 #undef OPTION_C6_STATE
1035 #define OPTION_C6_STATE TRUE
1036 #undef OPTION_IO_CSTATE
1037 #define OPTION_IO_CSTATE TRUE
1038 #undef OPTION_CPB
1039 #define OPTION_CPB TRUE
1040 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1041 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
1042 #undef OPTION_S3_MEM_SUPPORT
1043 #define OPTION_S3_MEM_SUPPORT TRUE
1044 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1045 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1046 #undef OPTION_CPU_CORELEVLING
1047 #define OPTION_CPU_CORELEVLING TRUE
1048 #undef OPTION_CPU_CFOH
1049 #define OPTION_CPU_CFOH TRUE
1050 #undef OPTION_MSG_BASED_C1E
1051 #define OPTION_MSG_BASED_C1E TRUE
1052 #undef OPTION_UDIMMS
1053 #define OPTION_UDIMMS TRUE
1054 #undef OPTION_RDIMMS
1055 #define OPTION_RDIMMS TRUE
1056 #undef OPTION_LRDIMMS
1057 #define OPTION_LRDIMMS TRUE
1058 #undef OPTION_SODIMMS
1059 #define OPTION_SODIMMS TRUE
1060 #undef OPTION_DDR3
1061 #define OPTION_DDR3 TRUE
1062 #undef OPTION_ECC
1063 #define OPTION_ECC TRUE
1064 #undef OPTION_BANK_INTERLEAVE
1065 #define OPTION_BANK_INTERLEAVE TRUE
1066 #undef OPTION_DCT_INTERLEAVE
1067 #define OPTION_DCT_INTERLEAVE TRUE
1068 #undef OPTION_NODE_INTERLEAVE
1069 #define OPTION_NODE_INTERLEAVE TRUE
1070 #undef OPTION_MEM_RESTORE
1071 #define OPTION_MEM_RESTORE TRUE
1072 #undef OPTION_ONLINE_SPARE
1073 #define OPTION_ONLINE_SPARE TRUE
1074 #undef OPTION_DIMM_EXCLUDE
1075 #define OPTION_DIMM_EXCLUDE TRUE
1076 #endif
1077#endif
1078
1079#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
1080 #undef GNB_SUPPORT
1081 #define GNB_SUPPORT TRUE
1082#endif
1083
1084#define OPTION_ACPI_PSTATES TRUE
1085#define OPTION_WHEA TRUE
1086#define OPTION_DMI TRUE
1087#define OPTION_EARLY_SAMPLES FALSE
1088#define CFG_ACPI_PSTATES_PPC TRUE
1089#define CFG_ACPI_PSTATES_PCT TRUE
1090#define CFG_ACPI_PSTATES_PSD TRUE
1091#define CFG_ACPI_PSTATES_PSS TRUE
1092#define CFG_ACPI_PSTATES_XPSS TRUE
1093#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1094#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1095#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1096#define OPTION_ALIB TRUE
1097/*---------------------------------------------------------------------------
1098 * Processing the options: Second, process the user's selections
1099 *--------------------------------------------------------------------------*/
1100#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1101 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1102 #undef OPTION_MULTISOCKET
1103 #define OPTION_MULTISOCKET FALSE
1104 #endif
1105#endif
1106#ifdef BLDOPT_REMOVE_ECC_SUPPORT
1107 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1108 #undef OPTION_ECC
1109 #define OPTION_ECC FALSE
1110 #endif
1111#endif
1112#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1113 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1114 #undef OPTION_UDIMMS
1115 #define OPTION_UDIMMS FALSE
1116 #endif
1117#endif
1118#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1119 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1120 #undef OPTION_RDIMMS
1121 #define OPTION_RDIMMS FALSE
1122 #endif
1123#endif
1124#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1125 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1126 #undef OPTION_SODIMMS
1127 #define OPTION_SODIMMS FALSE
1128 #endif
1129#endif
1130#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1131 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1132 #undef OPTION_LRDIMMS
1133 #define OPTION_LRDIMMS FALSE
1134 #endif
1135#endif
1136#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1137 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1138 #undef OPTION_BANK_INTERLEAVE
1139 #define OPTION_BANK_INTERLEAVE FALSE
1140 #endif
1141#endif
1142#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1143 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1144 #undef OPTION_DCT_INTERLEAVE
1145 #define OPTION_DCT_INTERLEAVE FALSE
1146 #endif
1147#endif
1148#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1149 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1150 #undef OPTION_NODE_INTERLEAVE
1151 #define OPTION_NODE_INTERLEAVE FALSE
1152 #endif
1153#endif
1154#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1155 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1156 #undef OPTION_PARALLEL_TRAINING
1157 #define OPTION_PARALLEL_TRAINING FALSE
1158 #endif
1159#endif
1160#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1161 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1162 #undef OPTION_ONLINE_SPARE
1163 #define OPTION_ONLINE_SPARE FALSE
1164 #endif
1165#endif
1166#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1167 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1168 #undef OPTION_MEM_RESTORE
1169 #define OPTION_MEM_RESTORE FALSE
1170 #endif
1171#endif
1172#ifdef BLDOPT_REMOVE_ACPI_PSTATES
1173 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1174 #undef OPTION_ACPI_PSTATES
1175 #define OPTION_ACPI_PSTATES FALSE
1176 #endif
1177#endif
1178#ifdef BLDOPT_REMOVE_SRAT
1179 #if BLDOPT_REMOVE_SRAT == TRUE
1180 #undef OPTION_SRAT
1181 #define OPTION_SRAT FALSE
1182 #endif
1183#endif
1184#ifdef BLDOPT_REMOVE_SLIT
1185 #if BLDOPT_REMOVE_SLIT == TRUE
1186 #undef OPTION_SLIT
1187 #define OPTION_SLIT FALSE
1188 #endif
1189#endif
1190#ifdef BLDOPT_REMOVE_WHEA
1191 #if BLDOPT_REMOVE_WHEA == TRUE
1192 #undef OPTION_WHEA
1193 #define OPTION_WHEA FALSE
1194 #endif
1195#endif
1196#ifdef BLDOPT_REMOVE_DMI
1197 #if BLDOPT_REMOVE_DMI == TRUE
1198 #undef OPTION_DMI
1199 #define OPTION_DMI FALSE
1200 #endif
1201#endif
1202#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1203 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1204 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1205 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1206 #endif
1207#endif
1208
1209#ifdef BLDOPT_REMOVE_HT_ASSIST
1210 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1211 #undef OPTION_HT_ASSIST
1212 #define OPTION_HT_ASSIST FALSE
1213 #endif
1214#endif
1215
1216#ifdef BLDOPT_REMOVE_ATM_MODE
1217 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1218 #undef OPTION_ATM_MODE
1219 #define OPTION_ATM_MODE FALSE
1220 #endif
1221#endif
1222
1223#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1224 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1225 #undef OPTION_MSG_BASED_C1E
1226 #define OPTION_MSG_BASED_C1E FALSE
1227 #endif
1228#endif
1229
1230#ifdef BLDOPT_REMOVE_C6_STATE
1231 #if BLDOPT_REMOVE_C6_STATE == TRUE
1232 #undef OPTION_C6_STATE
1233 #define OPTION_C6_STATE FALSE
1234 #endif
1235#endif
1236
1237#ifdef BLDOPT_REMOVE_GFX_RECOVERY
1238 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1239 #undef OPTION_GFX_RECOVERY
1240 #define OPTION_GFX_RECOVERY FALSE
1241 #endif
1242#endif
1243
1244#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1245 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1246 #undef CFG_ACPI_PSTATES_PPC
1247 #define CFG_ACPI_PSTATES_PPC FALSE
1248 #endif
1249#endif
1250
1251#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1252 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1253 #undef CFG_ACPI_PSTATES_PCT
1254 #define CFG_ACPI_PSTATES_PCT FALSE
1255 #endif
1256#endif
1257
1258#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1259 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1260 #undef CFG_ACPI_PSTATES_PSD
1261 #define CFG_ACPI_PSTATES_PSD FALSE
1262 #endif
1263#endif
1264
1265#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1266 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1267 #undef CFG_ACPI_PSTATES_PSS
1268 #define CFG_ACPI_PSTATES_PSS FALSE
1269 #endif
1270#endif
1271
1272#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1273 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1274 #undef CFG_ACPI_PSTATES_XPSS
1275 #define CFG_ACPI_PSTATES_XPSS FALSE
1276 #endif
1277#endif
1278
1279#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1280 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1281 #undef CFG_ACPI_PSTATE_PSD_INDPX
1282 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1283 #endif
1284#endif
1285
1286#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1287 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1288 #undef CFG_VRM_HIGH_SPEED_ENABLE
1289 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1290 #endif
1291#endif
1292
1293#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1294 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1295 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1296 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1297 #endif
1298#endif
1299
1300#ifdef BLDCFG_STARTING_BUSNUM
1301 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1302#else
1303 #define CFG_STARTING_BUSNUM (0)
1304#endif
1305
1306#ifdef BLDCFG_AMD_PLATFORM_TYPE
1307 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1308#else
1309 #define CFG_AMD_PLATFORM_TYPE 0
1310#endif
1311
1312CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
1313
1314#ifdef BLDCFG_MAXIMUM_BUSNUM
1315 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1316#else
1317 #define CFG_MAXIMUM_BUSNUM (0xF8)
1318#endif
1319
1320#ifdef BLDCFG_ALLOCATED_BUSNUM
1321 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1322#else
1323 #define CFG_ALLOCATED_BUSNUM (0x20)
1324#endif
1325
1326#ifdef BLDCFG_BUID_SWAP_LIST
1327 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1328#else
1329 #define CFG_BUID_SWAP_LIST (NULL)
1330#endif
1331
1332#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1333 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1334#else
1335 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1336#endif
1337
1338#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1339 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1340#else
1341 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1342#endif
1343
1344#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1345 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1346#else
1347 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1348#endif
1349
1350#ifdef BLDCFG_BUS_NUMBERS_LIST
1351 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1352#else
1353 #define CFG_BUS_NUMBERS_LIST (NULL)
1354#endif
1355
1356#ifdef BLDCFG_IGNORE_LINK_LIST
1357 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1358#else
1359 #define CFG_IGNORE_LINK_LIST (NULL)
1360#endif
1361
1362#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1363 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1364#else
1365 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1366#endif
1367
1368#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1369 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1370#else
1371 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1372#endif
1373
1374#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1375 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1376#else
1377 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1378#endif
1379
1380#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1381 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1382#else
1383 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1384#endif
1385
1386#ifdef BLDCFG_USE_HT_ASSIST
1387 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1388#else
1389 #define CFG_USE_HT_ASSIST (TRUE)
1390#endif
1391
1392#ifdef BLDCFG_USE_ATM_MODE
1393 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1394#else
1395 #define CFG_USE_ATM_MODE (TRUE)
1396#endif
1397
1398#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1399 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1400#else
1401 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1402#endif
1403
1404#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1405 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1406#else
1407 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1408#endif
1409
1410#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1411 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1412#else
1413 #define CFG_VRM_ADDITIONAL_DELAY (0)
1414#endif
1415
1416#ifdef BLDCFG_VRM_CURRENT_LIMIT
1417 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1418#else
1419 #define CFG_VRM_CURRENT_LIMIT 0
1420#endif
1421
1422#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1423 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1424#else
1425 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1426#endif
1427
1428#ifdef BLDCFG_VRM_SLEW_RATE
1429 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1430#else
1431 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1432#endif
1433
1434#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1435 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1436#else
1437 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
1438#endif
1439
1440#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1441 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1442#else
1443 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1444#endif
1445
1446#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1447 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1448#else
1449 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1450#endif
1451
1452#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1453 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1454#else
1455 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1456#endif
1457
1458#ifdef BLDCFG_VRM_NB_SLEW_RATE
1459 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1460#else
1461 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1462#endif
1463
1464#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1465 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1466#else
1467 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
1468#endif
1469
1470
1471#ifdef BLDCFG_PLAT_NUM_IO_APICS
1472 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1473#else
1474 #define CFG_PLAT_NUM_IO_APICS 0
1475#endif
1476
1477#ifdef BLDCFG_MEM_INIT_PSTATE
1478 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1479#else
1480 #define CFG_MEM_INIT_PSTATE 0
1481#endif
1482
1483#ifdef BLDCFG_PLATFORM_C1E_MODE
1484 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1485#else
1486 #define CFG_C1E_MODE C1eModeDisabled
1487#endif
1488
1489#ifdef BLDCFG_PLATFORM_C1E_OPDATA
1490 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1491#else
1492 #define CFG_C1E_OPDATA 0
1493#endif
1494
1495#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1496 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1497#else
1498 #define CFG_C1E_OPDATA1 0
1499#endif
1500
1501#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1502 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1503#else
1504 #define CFG_C1E_OPDATA2 0
1505#endif
1506
1507#ifdef BLDCFG_PLATFORM_CSTATE_MODE
1508 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1509#else
1510 #define CFG_CSTATE_MODE CStateModeDisabled
1511#endif
1512
1513#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1514 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1515#else
1516 #define CFG_CSTATE_OPDATA 0
1517#endif
1518
1519#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1520 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1521#else
1522 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1523#endif
1524
1525#ifdef BLDCFG_PLATFORM_CPB_MODE
1526 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1527#else
1528 #define CFG_CPB_MODE CpbModeAuto
1529#endif
1530
1531#ifdef BLDCFG_CORE_LEVELING_MODE
1532 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1533#else
1534 #define CFG_CORE_LEVELING_MODE 0
1535#endif
1536
1537#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1538 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1539#else
1540 #define CFG_AMD_PSTATE_CAP_VALUE 0
1541#endif
1542
1543#ifdef BLDCFG_HEAP_DRAM_ADDRESS
1544 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1545#else
1546 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1547#endif
1548
1549#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1550 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1551#else
1552 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1553#endif
1554
1555#ifdef BLDCFG_MEMORY_MODE_UNGANGED
1556 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1557#else
1558 #define CFG_MEMORY_MODE_UNGANGED TRUE
1559#endif
1560
1561#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1562 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1563#else
1564 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
1565#endif
1566
1567#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1568 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
1569#else
1570 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
1571#endif
1572
1573#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1574 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
1575#else
1576 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
1577#endif
1578
1579#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1580 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
1581#else
1582 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
1583#endif
1584
1585#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1586 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
1587#else
1588 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1589#endif
1590
1591#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1592 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1593#else
1594 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1595#endif
1596
1597#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1598 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1599#else
1600 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1601#endif
1602
1603#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1604 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1605#else
1606 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1607#endif
1608
1609#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1610 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1611#else
1612 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1613#endif
1614
1615#ifdef BLDCFG_MEMORY_POWER_DOWN
1616 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1617#else
1618 #define CFG_MEMORY_POWER_DOWN FALSE
1619#endif
1620
1621#ifdef BLDCFG_POWER_DOWN_MODE
1622 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1623#else
1624 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1625#endif
1626
1627#ifdef BLDCFG_ONLINE_SPARE
1628 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1629#else
1630 #define CFG_ONLINE_SPARE FALSE
1631#endif
1632
1633#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1634 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1635#else
1636 #define CFG_MEMORY_PARITY_ENABLE FALSE
1637#endif
1638
1639#ifdef BLDCFG_BANK_SWIZZLE
1640 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1641#else
1642 #define CFG_BANK_SWIZZLE TRUE
1643#endif
1644
1645#ifdef BLDCFG_TIMING_MODE_SELECT
1646 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1647#else
1648 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1649#endif
1650
1651#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1652 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1653#else
1654 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1655#endif
1656
1657#ifdef BLDCFG_DQS_TRAINING_CONTROL
1658 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1659#else
1660 #define CFG_DQS_TRAINING_CONTROL TRUE
1661#endif
1662
1663#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1664 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1665#else
1666 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1667#endif
1668
1669#ifdef BLDCFG_USE_BURST_MODE
1670 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1671#else
1672 #define CFG_USE_BURST_MODE FALSE
1673#endif
1674
1675#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1676 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1677#else
1678 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1679#endif
1680
1681#ifdef BLDCFG_ENABLE_ECC_FEATURE
1682 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1683#else
1684 #define CFG_ENABLE_ECC_FEATURE TRUE
1685#endif
1686
1687#ifdef BLDCFG_ECC_REDIRECTION
1688 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1689#else
1690 #define CFG_ECC_REDIRECTION FALSE
1691#endif
1692
1693#ifdef BLDCFG_SCRUB_DRAM_RATE
1694 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1695#else
1696 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1697#endif
1698
1699#ifdef BLDCFG_SCRUB_L2_RATE
1700 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1701#else
1702 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1703#endif
1704
1705#ifdef BLDCFG_SCRUB_L3_RATE
1706 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1707#else
1708 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1709#endif
1710
1711#ifdef BLDCFG_SCRUB_IC_RATE
1712 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1713#else
1714 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1715#endif
1716
1717#ifdef BLDCFG_SCRUB_DC_RATE
1718 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1719#else
1720 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1721#endif
1722
1723#ifdef BLDCFG_ECC_SYNC_FLOOD
1724 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1725#else
1726 #define CFG_ECC_SYNC_FLOOD 0
1727#endif
1728
1729#ifdef BLDCFG_ECC_SYMBOL_SIZE
1730 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1731#else
1732 #define CFG_ECC_SYMBOL_SIZE 0
1733#endif
1734
1735#ifdef BLDCFG_1GB_ALIGN
1736 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1737#else
1738 #define CFG_1GB_ALIGN FALSE
1739#endif
1740
1741#ifdef BLDCFG_UMA_ALLOCATION_MODE
1742 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1743#else
1744 #define CFG_UMA_MODE UMA_AUTO
1745#endif
1746
1747#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1748 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1749#else
1750 #define CFG_UMA_SIZE 0
1751#endif
1752
1753#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1754 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1755#else
1756 #define CFG_UMA_ABOVE4G FALSE
1757#endif
1758
1759#ifdef BLDCFG_UMA_ALIGNMENT
1760 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1761#else
1762 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1763#endif
1764
1765#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1766 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1767#else
1768 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1769#endif
1770
1771#ifdef BLDCFG_S3_LATE_RESTORE
1772 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1773#else
1774 #define CFG_S3_LATE_RESTORE TRUE
1775#endif
1776
1777#ifdef BLDCFG_USE_32_BYTE_REFRESH
1778 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1779#else
1780 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1781#endif
1782
1783#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1784 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1785#else
1786 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1787#endif
1788
1789#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1790 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1791#else
1792 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1793#endif
1794
1795#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1796 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1797#else
1798 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1799#endif
1800
1801#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1802 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1803#else
1804 #define CFG_GNB_HD_AUDIO TRUE
1805#endif
1806
1807#ifdef BLDCFG_CFG_ABM_SUPPORT
1808 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1809#else
1810 #define CFG_ABM_SUPPORT FALSE
1811#endif
1812
1813#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1814 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1815#else
1816 #define CFG_DYNAMIC_REFRESH_RATE 0
1817#endif
1818
1819#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1820 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1821#else
1822 #define CFG_LCD_BACK_LIGHT_CONTROL 0
1823#endif
1824
1825#ifdef BLDCFG_STEREO_3D_PINOUT
1826 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1827#else
1828 #define CFG_GNB_STEREO_3D_PINOUT 0
1829#endif
1830
1831#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1832 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1833#else
1834 #define CFG_GNB_IGPU_SSID 0
1835#endif
1836
1837#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1838 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1839#else
1840 #define CFG_GNB_HDAUDIO_SSID 0
1841#endif
1842
1843#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1844 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1845#else
1846 #define CFG_GNB_PCIE_SSID 0x12341022
1847#endif
1848
1849#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1850 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1851#else
1852 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1853#endif
1854
1855#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1856 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1857#else
1858 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1859#endif
1860
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1861#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1862 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1863#else
1864 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1865#endif
1866
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1867#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1868 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1869#else
1870 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1871#endif
1872
1873#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1874 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1875 #undef OPTION_EARLY_SAMPLES
1876 #define OPTION_EARLY_SAMPLES FALSE
1877 #else
1878 #undef OPTION_EARLY_SAMPLES
1879 #define OPTION_EARLY_SAMPLES TRUE
1880 #endif
1881#endif
1882
1883#ifdef BLDOPT_REMOVE_ALIB
1884 #if BLDOPT_REMOVE_ALIB == TRUE
1885 #undef OPTION_ALIB
1886 #define OPTION_ALIB FALSE
1887 #else
1888 #undef OPTION_ALIB
1889 #define OPTION_ALIB TRUE
1890 #endif
1891#endif
1892
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1893#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1894 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1895#else
1896 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1897#endif
1898
1899#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1900 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1901#else
1902 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1903#endif
1904
1905#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1906 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1907#else
1908 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1909#endif
1910
1911#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1912 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1913#else
1914 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1915#endif
1916
1917#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1918 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1919#else
1920 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1921#endif
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1922
1923#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1924 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1925#else
1926 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1927#endif
1928
1929#ifdef BLDCFG_PCI_MMIO_BASE
1930 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
1931#else
1932 #define CFG_PCI_MMIO_BASE (0)
1933#endif
1934
1935#ifdef BLDCFG_PCI_MMIO_SIZE
1936 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
1937#else
1938 #define CFG_PCI_MMIO_SIZE (0)
1939#endif
1940
1941#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1942 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1943#else
1944 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
1945#endif
1946
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1947/*---------------------------------------------------------------------------
1948 * Processing the options: Third, perform the option cross checks
1949 *--------------------------------------------------------------------------*/
1950// Assure that at least one type of memory support is included
1951#if OPTION_UDIMMS == FALSE
1952 #if OPTION_RDIMMS == FALSE
1953 #if OPTION_SODIMMS == FALSE
1954 #if OPTION_LRDIMMS == FALSE
1955 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1956 #endif
1957 #endif
1958 #endif
1959#endif
1960// Ensure at least one dimm type is capable
1961#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1962 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1963 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1964 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1965 #error BLDCFG: No dimm type is capable
1966 #endif
1967 #endif
1968 #endif
1969#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1970// Turn off multi-socket based features if only one node...
1971#if OPTION_MULTISOCKET == FALSE
1972 #undef OPTION_PARALLEL_TRAINING
1973 #define OPTION_PARALLEL_TRAINING FALSE
1974 #undef OPTION_NODE_INTERLEAVE
1975 #define OPTION_NODE_INTERLEAVE FALSE
1976#endif
1977// Ensure that at least one write leveling option is selected
1978#if OPTION_DDR3 == TRUE
1979 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
1980 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
1981 #error No Write leveling option selected for DDR3
1982 #endif
1983 #endif
1984 #if OPTION_SW_DRAM_INIT == FALSE
1985 #error Software dram init must be enabled for DDR3 dimms
1986 #endif
1987#endif
1988// Ensure at least one DQS receiver training option is selected
1989#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
1990 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1991 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1992 #error No DQS receiver training option has been slected
1993 #endif
1994 #endif
1995#endif
1996// Ensure at least one Rd Wr position training option has been selected
1997#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
1998 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
1999 #error No Rd Wr position training option has been selected
2000 #endif
2001#endif
2002// Ensure at least one dram init option has been selected
2003#if OPTION_HW_DRAM_INIT == FALSE
2004 #if OPTION_SW_DRAM_INIT == FALSE
2005 #error No Dram init option has been selected
2006 #endif
2007#endif
2008// Ensure the frequency limit is valid
2009#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2010 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2011 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2012 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2013 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2014 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2015 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2016 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2017 #error BLDCFG: Unsupported memory bus frequency
2018 #endif
2019 #endif
2020 #endif
2021 #endif
2022 #endif
2023 #endif
2024 #endif
2025#endif
2026// Ensure timing mode is valid
2027#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2028 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2029 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2030 #error BLDCFG: Invalid timing mode is set
2031 #endif
2032 #endif
2033#endif
2034// Ensure the scrub rate is valid
2035#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2036 #error BLDCFG: Unsupported dram scrub rate set
2037#endif
2038#if CFG_SCRUB_L2_RATE > 0x16
2039 #error BLDCFG: Unsupported L2 scrubber rate set
2040#endif
2041#if CFG_SCRUB_L3_RATE > 0x16
2042 #error BLDCFG: unsupported L3 scrubber rate set
2043#endif
2044#if CFG_SCRUB_IC_RATE > 0x16
2045 #error BLDCFG: Unsupported Instruction cache scrub rate set
2046#endif
2047#if CFG_SCRUB_DC_RATE > 0x16
2048 #error BLDCFG: Unsupported Dcache scrub rate set
2049#endif
2050// Ensure Quad rank dimm type is valid
2051#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2052 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2053 #error BLDCFG: Invalid quad rank dimm type set
2054 #endif
2055#endif
2056// Ensure ECC symbol size is valid
2057#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2058 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2059 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2060 #error BLDCFG: Invalid Ecc symbol size set
2061 #endif
2062 #endif
2063#endif
2064// Ensure power down mode is valid
2065#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2066 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2067 #error BLDCFG: Invalid power down mode set
2068 #endif
2069#endif
2070
2071/*****************************************************************************
2072 *
2073 * Process the option logic, setting local control variables
2074 *
2075 ****************************************************************************/
2076#if OPTION_ACPI_PSTATES == TRUE
2077 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2078 #define OPTFCN_GATHER_DATA PStateGatherData
2079 #if OPTION_MULTISOCKET == TRUE
2080 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2081 #else
2082 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2083 #endif
2084#else
2085 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2086 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2087 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2088#endif
2089
2090
2091/*****************************************************************************
2092 *
2093 * Include the structure definitions for the defaults table structures
2094 *
2095 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]2096#include <CommonReturns.h>
2097#include <agesa-entry-cfg.h>
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2098#include "Options.h"
2099#include "OptionCpuFamiliesInstall.h"
2100#include "OptionsHt.h"
2101#include "OptionHtInstall.h"
2102#include "OptionMemory.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2103#include "OptionMemoryInstall.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2104#include "OptionCpuFeaturesInstall.h"
2105#include "OptionDmi.h"
2106#include "OptionDmiInstall.h"
2107#include "OptionPstate.h"
2108#include "OptionPstateInstall.h"
2109#include "OptionWhea.h"
2110#include "OptionWheaInstall.h"
2111#include "OptionSrat.h"
2112#include "OptionSratInstall.h"
2113#include "OptionSlit.h"
2114#include "OptionSlitInstall.h"
2115#include "OptionMultiSocket.h"
2116#include "OptionMultiSocketInstall.h"
2117#include "OptionIdsInstall.h"
2118#include "OptionGfxRecovery.h"
2119#include "OptionGfxRecoveryInstall.h"
2120#include "OptionGnb.h"
2121#include "OptionGnbInstall.h"
2122#include "OptionS3ScriptInstall.h"
2123
2124
2125/*****************************************************************************
2126 *
2127 * Generate the output structures (defaults tables)
2128 *
2129 ****************************************************************************/
2130BUILD_OPT_CFG UserOptions = {
2131 { // AGESA version string
2132 AGESA_CODE_SIGNATURE, // code header Signature
2133 AGESA_PACKAGE_STRING, // 8 character ID
2134 AGESA_VERSION_STRING, // 12 character version string
2135 0 // null string terminator
2136 },
2137 //Build Option Area
2138 OPTION_UDIMMS, //UDIMMS
2139 OPTION_RDIMMS, //RDIMMS
2140 OPTION_LRDIMMS, //LRDIMMS
2141 OPTION_ECC, //ECC
2142 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
2143 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
2144 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
2145 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
2146 OPTION_ONLINE_SPARE, //ONLINE_SPARE
2147 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
2148 OPTION_MULTISOCKET, //MULTISOCKET
2149 OPTION_ACPI_PSTATES, //ACPI_PSTATES
2150 OPTION_SRAT, //SRAT
2151 OPTION_SLIT, //SLIT
2152 OPTION_WHEA, //WHEA
2153 OPTION_DMI, //DMI
2154 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
2155 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
2156
2157 //Build Configuration Area
2158 CFG_PCI_MMIO_BASE,
2159 CFG_PCI_MMIO_SIZE,
2160 {
2161 // CoreVrm
2162 {
2163 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
2164 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
2165 CFG_VRM_SLEW_RATE, // VrmSlewRate
2166 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
2167 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
2168 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
2169 },
2170 // NbVrm
2171 {
2172 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
2173 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
2174 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
2175 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
2176 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
2177 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
2178 }
2179 },
2180 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
2181 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
2182 CFG_C1E_MODE, //C1eMode
2183 CFG_C1E_OPDATA, //C1ePlatformData
2184 CFG_C1E_OPDATA1, //C1ePlatformData1
2185 CFG_C1E_OPDATA2, //C1ePlatformData2
2186 CFG_CSTATE_MODE, //CStateMode
2187 CFG_CSTATE_OPDATA, //CStatePlatformData
2188 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
2189 CFG_CPB_MODE, //CpbMode
2190 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
2191 {
2192 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
2193 CFG_USE_HT_ASSIST, // CfgUseHtAssist
2194 CFG_USE_ATM_MODE, // CfgUseAtmMode
2195 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
2196 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2197 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2198 },
2199 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
2200 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
2201 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
2202
2203 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
2204 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
2205 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
2206 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
2207 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
2208 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
2209 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
2210 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
2211 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
2212 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
2213 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
2214 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
2215 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
2216 CFG_ONLINE_SPARE, // CfgOnlineSpare
2217 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
2218 CFG_BANK_SWIZZLE, // CfgBankSwizzle
2219 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
2220 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
2221 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
2222 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
2223 CFG_USE_BURST_MODE, // CfgUseBurstMode
2224 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
2225 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
2226 CFG_ECC_REDIRECTION, // CfgEccRedirection
2227 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
2228 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
2229 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
2230 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
2231 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
2232 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
2233 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
2234 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
2235 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
2236 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
2237 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
2238 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
2239 CFG_UMA_MODE, // CfgUmaMode
2240 CFG_UMA_SIZE, // CfgUmaSize
2241 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
2242 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
2243 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
2244 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
2245 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
2246 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
2247 CFG_ABM_SUPPORT, // CfgAbmSupport
2248 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
2249 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
2250 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
2251 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
2252 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
2253 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
2254 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
2255 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
2256 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
2257
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]2258 {{
2259 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
2260 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
2261 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2262 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2263 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
2264 }},
2265 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2266 0, //reserved...
2267};
2268
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2269
2270CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2271{
2272 IDS_LATE_RUN_AP_TASK
2273 // Get DMI info
2274 CPU_DMI_AP_GET_TYPE4_TYPE7
2275 // Probe filter enable
2276 HT_ASSIST_AP_DISABLE_CACHE
2277 HT_ASSIST_AP_ENABLE_CACHE
2278
2279 { 0, NULL }
2280};
2281
2282#if AGESA_ENTRY_INIT_RESET == TRUE
2283 #if IDSOPT_IDS_ENABLED == TRUE
2284 #if IDSOPT_TRACING_ENABLED == TRUE
2285 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2286 CONST CHAR8 *BldOptDebugOutput[] = {
2287 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2288 //Build Option Area
2289 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2290 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2291 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2292 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2293 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2294 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2295 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2296 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2297 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2298 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2299 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2300 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2301 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2302 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2303 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2304 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2305 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2306 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2307
2308 //Build Configuration Area
2309 // CoreVrm
2310 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2311 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2312 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2313 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
2314 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2315 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
2316 // NbVrm
2317 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2318 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2319 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2320 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
2321 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2322 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
2323
2324 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2325 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2326 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2327 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2328 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2329 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2330 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2331 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2332 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2333 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2334 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2335
2336 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2337 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2338 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2339 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2340 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2341 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2342
2343 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2344
2345 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2346 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2347 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2348 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
2349
2350 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2351 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2352 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2353
2354 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2355 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2356 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2357 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2358 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2359 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2360 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2361 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2362 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2363 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2364 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2365
2366 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2367 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2368 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2369 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2370 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2371 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2372 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2373 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2374
2375 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2376 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2377 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2378 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2379
2380 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2381 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2382 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2383 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2384 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2385 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2386 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2387 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2388 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2389 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2390 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2391
2392 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2393 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2394
2395 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2396
2397 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2398 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2399 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2400 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2401 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2402 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2403 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2404 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2405 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2406 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
2407 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
2408 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
2409
2410 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
2411 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]2412 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2413 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2414 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2415 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2416 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2417 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2418 #endif
2419 NULL
2420 };
2421 #endif
2422 #endif
2423#endif